Patents by Inventor Shinichi Jinbo
Shinichi Jinbo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105737Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.Type: ApplicationFiled: December 11, 2023Publication date: March 28, 2024Inventors: Hisao IKEDA, Kouhei TOYOTAKA, Hideaki SHISHIDO, Hiroyuki MIYAKE, Kohei YOKOYAMA, Yasuhiro JINBO, Yoshitaka DOZEN, Takaaki NAGATA, Shinichi HIRASA
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Patent number: 6784718Abstract: An input circuit includes a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit.Type: GrantFiled: August 30, 2002Date of Patent: August 31, 2004Assignee: Renesas Technology Corp.Inventors: Takeo Okamoto, Tadaaki Yamauchi, Shinichi Jinbo, Makoto Suwa, Junko Matsumoto
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Patent number: 6724679Abstract: A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.Type: GrantFiled: April 22, 2002Date of Patent: April 20, 2004Assignee: Renesas Technology Corp.Inventors: Tsutomu Nagasawa, Hideki Yonetani, Kozo Ishida, Shinichi Jinbo, Makoto Suwa, Tadaaki Yamauchi, Junko Matsumoto, Zengcheng Tian, Takeo Okamoto
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Patent number: 6625050Abstract: Pad lines are placed on the peripheral region of a chip along EAST band and WEST band (E/W band). In order to allow the chip with pads arranged on the peripheral region to be adaptable to a TSOP, VDD and VSS pads are arranged on the edge region on NORTH band and SOUTH band (N/S band) near the center of the N/S band. Moreover, in consideration of frame design for the TSOP, some pads on the ends of the pad lines among the pads included in the pad lines are arranged in reverse order relative to the order of pins. Further, VDDQ and VSSQ pads are arranged in the same order as that of pins for a package which requires no consideration of frame design. On the other hand, for use in a BGA package, VDD and VSS pads are arranged in pairs at respective ends of the pad lines. A semiconductor memory device with this pad arrangement is accordingly adaptable to various types of packages.Type: GrantFiled: May 14, 2002Date of Patent: September 23, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Makoto Suwa, Shinichi Jinbo, Zengcheng Tian, Takeo Okamoto, Kozo Ishida, Hideki Yonetani, Tsutomu Nagasawa, Tadaaki Yamauchi, Junko Matsumoto
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Publication number: 20030080795Abstract: An input circuit is comprised of a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit. Even if the output power supply voltage varies to cause the input signal to change, whether the input signal is at H level or L level can accurately be determined and an internal signal is generated correctly.Type: ApplicationFiled: August 30, 2002Publication date: May 1, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takeo Okamoto, Tadaaki Yamauchi, Shinichi Jinbo, Makoto Suwa, Junko Matsumoto
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Publication number: 20030081490Abstract: A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.Type: ApplicationFiled: April 22, 2002Publication date: May 1, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tsutomu Nagasawa, Hideki Yonetani, Kozo Ishida, Shinichi Jinbo, Makoto Suwa, Tadaaki Yamauchi, Junko Matsumoto, Zengcheng Tian, Takeo Okamoto
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Publication number: 20030081443Abstract: Pad lines are placed on the peripheral region of a chip along EAST band and WEST band (E/W band). In order to allow the chip with pads arranged on the peripheral region to be adaptable to a TSOP, VDD and VSS pads are arranged on the edge region on NORTH band and SOUTH band (N/S band) near the center of the N/S band. Moreover, in consideration of frame design for the TSOP, some pads on the ends of the pad lines among the pads included in the pad lines are arranged in reverse order relative to the order of pins. Further, VDDQ and VSSQ pads are arranged in the same order as that of pins for a package which requires no consideration of frame design. On the other hand, for use in a BGA package, VDD and VSS pads are arranged in pairs at respective ends of the pad lines. A semiconductor memory device with this pad arrangement is accordingly adaptable to various types of packages.Type: ApplicationFiled: May 14, 2002Publication date: May 1, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Makoto Suwa, Shinichi Jinbo, Zengcheng Tian, Takeo Okamoto, Kozo Ishida, Hideki Yonetani, Tsutomu Nagasawa, Tadaaki Yamauchi, Junko Matsumoto
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Patent number: 6121806Abstract: A level adjusting circuit for controlling a voltage supplied to a load such as a semiconductor device, which comprises a voltage level detecting circuit, a reference potential generating circuit for generating a pair of reference potential values to be output into the voltage level detecting circuit, and a monitor pad for drawing out the voltage supplied to the load, wherein the reference potential values are respectively used to compare with the voltage to thereby output a signal for starting supply of the voltage and a signal for ceasing the supply of the voltage under a usually used condition; and the voltage level detecting circuit is to compare either one of the reference potential values with the voltage or the other reference potential value with the voltage at a time under a testing condition, whereby the reference potential generating circuit can accurately be adjusted to change the reference potential values to render the voltage in a range permissible for operation of the load.Type: GrantFiled: October 6, 1998Date of Patent: September 19, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Kono, Takayuki Miyamoto, Katsuyoshi Mitsui, Shinichi Jinbo
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Patent number: 5608682Abstract: An address generating circuit and an address switching circuit of a DRAM output address signals A0 to A11 according to a refresh cycle time set by the user being less than a predetermined value, and output address signals A0 to A10 according to the refresh cycle time being the predetermined value or more. A row decoder selects one word line in response to the signals A0 to A11, and selects two word lines in response to the signals A0 to A10. Since refresh is carried out by selecting two word lines when the refresh cycle time is at the predetermined value or more, disappearance of data can be prevented.Type: GrantFiled: November 7, 1995Date of Patent: March 4, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shinichi Jinbo, Shigeru Mori
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Patent number: 5587648Abstract: An internal power supply circuit of the present invention includes a primary internal power supply potential supplying circuit, two auxiliary internal power supply potential supplying circuits, and a P channel MOS transistor. The internal power supply potential supplying circuit always supplies an internal power supply potential to a first output node based on an external power supply potential. One auxiliary internal power supply potential supplying circuit is activated in response to a control signal, and, when activated, supplies the internal power supply potential to the first output node. The other auxiliary internal power supply potential supplying circuit is activated in response to another control signal, and, when activated, supplies the internal power supply potential to a second output node. The P channel MOS transistor is connected between the first output node and the second output node. The P channel MOS transistor has a gate electrode receiving the control signal.Type: GrantFiled: January 25, 1995Date of Patent: December 24, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shinichi Jinbo, Shigeru Mori