Patents by Inventor Shinichi Kamagami

Shinichi Kamagami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010002047
    Abstract: A thin film transistor of this invention has a structure obtained by sequentially stacking, on an insulating substrate, a silicon nitride film, a silicon oxide film, a polysilicon thin film with a channel region and source and drain regions facing each other via the channel region, an insulating film, and a gate electrode. The boron concentration decreases from the channel region toward the silicon nitride film in the silicon oxide film region between the channel region and the silicon nitride film. The silicon oxide film region between the channel region and the silicon nitride film is made up of a first region which is in contact with the channel region and has a boron concentration of 1×1016 atoms/cm3 or more, and a second region between the first region and the silicon nitride film, which has a boron concentration of less than 1×1016 atoms/cm3. The first region has a thickness of 200 Å or less.
    Type: Application
    Filed: January 18, 2001
    Publication date: May 31, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mitsuaki Suzuki, Shinichi Kamagami, Takuji Nakazono
  • Patent number: 6201260
    Abstract: A thin film transistor of this invention has a structure obtained by sequentially stacking, on an insulating substrate, a silicon nitride film, a silicon oxide film, a polysilicon thin film with a channel region and source and drain regions facing each other via the channel region, an insulating film, and a gate electrode. The boron concentration decreases from the channel region toward the silicon nitride film in the silicon oxide film region between the channel region and the silicon nitride film. The silicon oxide film region between the channel region and the silicon nitride film is made up of a first region which is in contact with the channel region and has a boron concentration of 1×1016 atoms/cm3 or more, and a second region between the first region and the silicon nitride film, which has a boron concentration of less than 1×1016 atoms/cm3. The first region has a thickness of 200 Å or less.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: March 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuaki Suzuki, Shinichi Kamagami, Takuji Nakazono
  • Patent number: 5227901
    Abstract: A liquid crystal display device includes first and second substrate and a liquid crystal layer sealed between the substrates. A plurality of pixel elements are formed in a matrix pattern on the first substrate, and a plurality of driving nonlinear resistance elements are formed on the first substrate and electrically connected to the pixel electrodes, respectively. A plurality of parallel wiring electrodes are formed on the first substrate, respectively extending in parallel to the columns of the pixel electrodes, and electrically connected to the respective nonlinear resistance elements on the respective columns of the pixel electrodes. Each wiring electrode is divided at a dividing portion and has a pair of divided ends. Protecting nonlinear resistance elements are respectively formed on the divided ends of each wiring electrode so as to reduce potential difference between the divided ends when static electricity is generated at the dividing portions.
    Type: Grant
    Filed: March 19, 1992
    Date of Patent: July 13, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Iizuka, Shinichi Kamagami, Yasuhisa Oana
  • Patent number: 5204660
    Abstract: In a liquid crystal display device, MIM type nonlinear resistive swiching elements are connected to pixel electroes, respectively, counter electrodes are arranged to oppose the pixel electrodes and, a liquid crystal layer having a threshould voltage Vth (V) and a saturation voltage Vsat (V) is arranged between the pixel electrodes and the counter electrodes. A voltage having a voltage waveform constituted by a select period in which the signal voltage is applied and a nonselect period in which the signal voltage is held is generated between said electrodes, and an absolute value Vb (V) of the voltage applied between said electrodes during the nonselect period satisfies a relation of:V'/2-0.4.ltoreq.Vb.ltoreq.V'/2+0.5(where V'=Vth+Vsat).
    Type: Grant
    Filed: October 4, 1991
    Date of Patent: April 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Kamagami, Hiroshi Morita
  • Patent number: 5032008
    Abstract: This invention discloses a liquid crystal display device including a liquid crystal cell having two substrates, arranged substantially parallel to each other, and having electrodes on their opposing surfaces, and a liquid crystal composition held between the substrates, first and second polarizers arranged at both sides of the liquid crystal cell, a first optical delay plate arranged between the liquid crystal cell and the second polarizer, and a second optical delay plate arranged between the first optical delay plate and the second polarizer, wherein liquid crystal molecules of the liquid crystal composition are arranged in twisted mode from a second polarizer side to a first polarizer side, the first and second optical delay plates are arranged such that optical axes thereof cross to form an acute angle, and a twist direction of the liquid crystal molecules in the state of twisted mode is the same as a direction from the optical axis of the second optical delay plate toward the first optical delay plate sh
    Type: Grant
    Filed: July 7, 1989
    Date of Patent: July 16, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomiaki Yamamoto, Akio Murayama, Susumu Kondo, Hitoshi Hato, Shinichi Kamagami, Shoichi Matsumoto
  • Patent number: 5018839
    Abstract: A liquid crystal display device has a liquid crystal cell including first and second substrates spatially arranged to oppose each other, first and second electrodes formed on opposing surfaces of the first and second substrates, respectively, and a liquid crystal composition filled between the first and second substrates and arranged in a twisted mode. First and second polarizers are arranged on both sides of the liquid crystal cell. An optical retardation film is arranged between the first substrate and the first polarizer. The optical retardation film has a retardation value falling within a range of RO.times.0.55 to RO.times.0.80 where RO is a retardation of the liquid crystal cell. An optical axis of the optical retardation film is angled 100.degree. to 130.degree. with respect to the alignment direction of the liquid crystal molecules on the first substrate.
    Type: Grant
    Filed: July 26, 1989
    Date of Patent: May 28, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomiaki Yamamoto, Akio Murayama, Susumu Kondo, Hitoshi Hato, Shinichi Kamagami, Shoichi Matsumoto
  • Patent number: 4995704
    Abstract: The present invention discloses a liquid crystal display device including a liquid crystal cell, the liquid crystal cell including two substrates which are arranged substantially parallel to each other and have electrodes on opposing surfaces thereof, and a liquid crystal composition held between the substrates such that the liquid crystal molecules are arranged in a twisted mode, first and second polarizers arranged at both sides of the liquid crystal cell, and first and second optical delay plates arranged between the liquid crystal cell and the second polarizer, wherein assuming that a retardation value of the liquid crystal cell is given by:R.sub.0 =.DELTA.n.multidot.d.multidot.cos.sup.2 .theta.where .DELTA.n is the optical anisotropy of the liquid crystal composition, d is the distance between the two substrates in the liquid crystal cell, and .theta. is the tilt angle of the liquid crystal composition, a total of the retardation values of the first and second optical delay plates is R.sub.0 .times.0.
    Type: Grant
    Filed: July 7, 1989
    Date of Patent: February 26, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomiaki Yamamoto, Akio Murayama, Susmu Kondo, Hitoshi Hato, Shinichi Kamagami, Shoichi Matsumoto
  • Patent number: 4984874
    Abstract: A liquid crystal cell includes first and second substrates arranged to oppose each other, first and second electrodes formed on opposing surfaces of the first and second substrates, respectively, and a liquid crystal composition filled between the first and second substrates and arranged in a twisted mode. First and second polarizers are arranged on both sides of the liquid crystal cell. A first optical retardation film is arranged between the first substrate and the first polarizer, and a second optical retardation film is arranged between said second substrate and said second polarizer. The liquid crystal cell has a retardation value R0 of 0.4 to 0.85 .mu.m, defined by an equation:.DELTA.n.multidot.d.multidot.cos.sup.2 .theta.where d is a distance between the first and second substrates, .DELTA.n is an optical anisotropy of the liquid crystal composition and .theta. is a tilt angle of the liquid crystal composition.
    Type: Grant
    Filed: July 7, 1989
    Date of Patent: January 15, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomiaki Yamamoto, Akio Murayama, Susumu Kondo, Hitoshi Hato, Shinichi Kamagami, Shoichi Matsumoto