Abstract: A semiconductor device includes a first semiconductor layer formed above a first region of a supporting substrate with a buried oxide layer disposed therebetween and a second semiconductor layer formed on a second region of the supporting substrate. An interface between the supporting substrate and the second semiconductor layer is placed in substantially the same depth position as the undersurface of the buried oxide layer or in a position deeper than the buried oxide layer.

Abstract: A semiconductor device includes a first semiconductor layer formed above a first region of a supporting substrate with a buried oxide layer disposed therebetween and a second semiconductor layer formed on a second region of the supporting substrate. An interface between the supporting substrate and the second semiconductor layer is placed in a position deeper than the buried oxide layer.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.

Abstract: A single crystal pulling apparatus for a metal fluoride comprising a crucible provided in a chamber and filling a molten solution of a single crystal manufacturing material, a melting heater provided to surround the crucible, a vertically movable single crystal pulling bar including a seed crystal on a tip and coming in contact with the molten solution of the single crystal manufacturing material filled in the crucible, a heat insulating wall provided in the chamber to surround at least a peripheral side portion of a single crystal pulling region in an upper part of the crucible, a ceiling board for closing an opening portion of an upper end in an upper part of the heat insulating wall, and a single crystal pulling chamber surrounded by the heat insulating wall and the ceiling board, wherein the ceiling board is provided with at least an inserting hole for inserting the single crystal pulling bar, and a coefficient of thermal conductivity in a direction of a thickness of the ceiling board is 1000 to 50000 W/m

Abstract: A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.

Abstract: A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

Abstract: A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.

Abstract: A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

Abstract: A semiconductor device includes a first semiconductor layer formed above a first region of a supporting substrate with a buried oxide layer disposed therebetween and a second semiconductor layer formed on a second region of the supporting substrate. An interface between the supporting substrate and the second semiconductor layer is placed in substantially the same depth position as the undersurface of the buried oxide layer or in a position deeper than the buried oxide layer.

Abstract: A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.

Abstract: In a vacuum pressure control system constituted of a vacuum vessel, a vacuum pump sucking gas in the vacuum vessel, a vacuum proportional opening and closing valve disposed on a pipe connecting the vacuum vessel and the vacuum pump, the vacuum proportional opening and closing valve changing its opening to change the vacuum pressure in the vacuum vessel, a pressure sensor to measure the vacuum pressure in the vacuum vessel and a vacuum pressure control device to control the opening of the vacuum proportional opening and closing valve based on the output of the pressure sensor, the vacuum proportional opening and closing valve is provided with a valve seat, a valve member with a tapered surface in its outer periphery and a pilot valve, the valve member being movable along a center line of the valve seat to change a clearance area between the valve seat and the tapered surface, and the vacuum pressure control device controls a servo valve to change the pressure of air to be supplied to the pilot valve based on t

Abstract: In a vacuum pressure control system constituted of a vacuum vessel, a vacuum pump sucking gas in the vacuum vessel, a vacuum proportional opening and closing valve disposed on a pipe connecting the vacuum vessel and the vacuum pump, the vacuum proportional opening and closing valve changing its opening to change the vacuum pressure in the vacuum vessel, a pressure sensor to measure the vacuum pressure in the vacuum vessel and a vacuum pressure control device to control the opening of the vacuum proportional opening and closing valve based on the output of the pressure sensor, the vacuum proportional opening and closing valve is provided with a valve seat, a valve member with a tapered surface in its outer periphery and a pilot valve, the valve member being movable along a center line of the valve seat to change a clearance area between the valve seat and the tapered surface, and the vacuum pressure control device controls a servo valve to change the pressure of air to be supplied to the pilot valve based on t

Abstract: A new solid nifedipine preparation which comprises (a) a particulate dry composition having been obtained by subjecting nifedipine in mixture with casein and one or more inorganic excipients to co-pulverization or (b) a particulate dry composition having been obtained by adding an enteric high molecular substance and a plasticizer optionally with a higher fatty acid ester to the co-pulverized mixture obtained above, subjecting the mixture to co-pulverization and then dry-processing the co-pulverized product to a pharmaceutically acceptable solid form, as well as a process for preparing the solid nifedipine preparation comprising a particulate dry composition (a) or (b) by the specific co-pulverization and a dry compounding method. The solid nifedipine preparation is excellent in dissolution of nifedipine or possesses a controlled dissolution rate of nifedipine.