Patents by Inventor Shinichi Shuto

Shinichi Shuto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120221773
    Abstract: The disclosed invention provides a technique for efficiently avoiding read disturbance. A nonvolatile semiconductor memory device includes a nonvolatile memory unit and a controller that can control refresh processing for rewriting data in a block of blocks assumed to be erasable units in the nonvolatile memory unit into anther block different from the block. The controller sets up a first area and a second area different from the first area in the nonvolatile memory unit and, each time a refresh trigger occurs, executes refresh processing for the first area and the second area, such that a refresh frequency of data in the first area will become higher than a refresh frequency of data in the second area. Thereby, it is possible to efficiently avoid read disturbance when read access is repeated.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 30, 2012
    Inventors: Shinichi SHUTO, Takayuki Tamura, Noriyuki Kotani, Hiroyasu Tominaga
  • Patent number: 7269748
    Abstract: Disclosed herewith is a semiconductor processing system such as a card type electronic device, which can easily cope with an error caused by power shutoff that occurs when the card is ejected. The semiconductor processing system is provided with an interface control circuit and a processing circuit and receives operation power from an external device such as a card slot when it is inserted therein. According to a first aspect of the present invention for coping with an error caused by power shutoff that occurs when the card is ejected, the interface control circuit, when the card is ejected from the card slot, detects a potential change to occur at a first external terminal to be disconnected from a predetermined terminal of the card slot before the power supply from the card slot is shut off, then instructs the processing circuit that is active to perform an ending processing. The semiconductor processing system can end the processing by itself before the power supply stops completely.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: September 11, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shinichi Shuto, Takayuki Tamura, Chiaki Kumahara
  • Publication number: 20070035998
    Abstract: Disclosed is a nonvolatile memory apparatus in which a nonvolatile memory and a controller are mounted and which realizes improved performance of read/write speeds and improved resistance to a retention error. A nonvolatile memory can store information of two bits or more, and can perform a first reading operation of outputting information read from a nonvolatile memory cell as 1-bit information and a second reading operation of outputting the read information as 2-bit information. A controller performs the first reading operation to read first information from the nonvolatile memory and performs the second reading operation to read second information. The reading speed of the first reading operation is faster than that of the second reading operation.
    Type: Application
    Filed: October 17, 2006
    Publication date: February 15, 2007
    Inventors: Takayuki Tamura, Yoshinori Takase, Shinichi Shuto, Yasuhiro Nakamura, Chiaki Kumahara
  • Publication number: 20040193928
    Abstract: Disclosed herewith is a semiconductor processing system such as a card type electronic device, which can easily cope with an error caused by power shutoff that occurs when the card is ejected. The semiconductor processing system is provided with an interface control circuit and a processing circuit and receives operation power from an external device such as a card slot when it is inserted therein. According to a first aspect of the present invention for coping with an error caused by power shutoff that occurs when the card is ejected, the interface control circuit, when the card is ejected from the card slot, detects a potential change to occur at a first external terminal to be disconnected from a predetermined terminal of the card slot before the power supply from the card slot is shut off, then instructs the processing circuit that is active to perform an ending processing. The semiconductor processing system can end the processing by itself before the power supply stops completely.
    Type: Application
    Filed: November 17, 2003
    Publication date: September 30, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Shinichi Shuto, Takayuki Tamura, Chiaki Kumahara
  • Publication number: 20040042269
    Abstract: Disclosed is a nonvolatile memory apparatus in which a nonvolatile memory and a controller are mounted and which realizes improved performance of read/write speeds and improved resistance to a retention error. A nonvolatile memory can store information of two bits or more, and can perform a first reading operation of outputting information read from a nonvolatile memory cell as 1-bit information and a second reading operation of outputting the read information as 2-bit information. A controller performs the first reading operation to read first information from the nonvolatile memory and performs the second reading operation to read second information. The reading speed of the first reading operation is faster than that of the second reading operation.
    Type: Application
    Filed: August 5, 2003
    Publication date: March 4, 2004
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takayuki Tamura, Yoshinori Takase, Shinichi Shuto, Yasuhiro Nakamura, Chiaki Kumahara