Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.

Abstract: A semiconductor device includes a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit line with turning the switch ON, so that the local bit line receives the precharge voltage through the global bit line and the switch, and after a lapse of a predetermined time, a precharge voltage is further supplied to the local bit line without an intervention of the global bit line and the switch.

Abstract: An echo cancellation apparatus is connectable to a speaker configured to output speaker signals and a microphone configured to receive a sound from the speaker and including a plurality of microphone elements. The echo cancellation apparatus includes: a generating unit configured to generate a plurality of sensitivity signals having different sensitivity patterns which represent directionality of the microphone, based on a plurality of microphone signals obtained from the respective microphone signals; a delay estimating unit configured to determine a shortest delay time as an estimated delay time, the shortest delay time being a shortest one of delay times between the speaker signals and the microphone signals, the delay times being obtained from the respective sensitivity signals; and an echo suppressing unit configured to suppress echoes of the plurality of microphone signals using the estimated delay time.

Abstract: An electronic endoscope signal-processing device is provided that includes a gradation compensation processor. The gradation compensation processor compensates for R, G and B gradations by controlling R, G and B tone curves defining relationship between input values and output values of each of the R, G and B signals. The R tone curve is shaped so as to squash the output values of the R signal when the R signal input values are in a relatively low range and to expand the output values when the input values are in a relatively high range. The G and B tone curves are shaped so squash the output value of the respective signals when the input signals are in high or low ranges, and the G tone curve and the B tone curve are identical.

Abstract: Disclosed herein is a semiconductor device comprising an array having a hierarchical bit line structure, global bit lines adjacent to each other, local bit lines corresponding to the global bit lines, hierarchical switches, precharge circuits precharging the global bit lines, precharge circuits precharging the local bit lines, and a control circuit. When performing a test of the array, precharge voltages for the global bit lines are set to potentials different from each other, and the control circuit controls the potentials to be applied to the local bit lines through the global bit lines and the hierarchical switches.

Abstract: A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.

Abstract: A device includes a semiconductor substrate, a first local bit line formed in the semiconductor substrate and elongated in a first direction, a first insulating layer on the semiconductor substrate, a first global bit line formed on the first insulating layer, a first path formed in the first insulating layer to couple a first end of the first local bit line with the first global bit line, and a second path formed in the first insulating layer to couple a second end of the first local bit line with the first global bit line.

Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.

Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.

Abstract: The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal.

Abstract: An echo cancellation apparatus is connectable to a speaker configured to output speaker signals and a microphone configured to receive a sound from the speaker and including a plurality of microphone elements. The echo cancellation apparatus includes: a generating unit configured to generate a plurality of sensitivity signals having different sensitivity patterns which represent directionality of the microphone, based on a plurality of microphone signals obtained from the respective microphone signals; a delay estimating unit configured to determine a shortest delay time as an estimated delay time, the shortest delay time being a shortest one of delay times between the speaker signals and the microphone signals, the delay times being obtained from the respective sensitivity signals; and an echo suppressing unit configured to suppress echoes of the plurality of microphone signals using the estimated delay time.

Abstract: An electronic endoscope signal-processing device is provided that includes a gradation compensation processor. The gradation compensation processor compensates for R, G and B gradations by controlling R, G and B tone curves defining relationship between input values and output values of each of the R, G and B signals. The R tone curve is shaped so as to squash the output values of the R signal when the R signal input values are in a relatively low range and to expand the output values when the input values are in a relatively high range. The G and B tone curves are shaped so squash the output value of the respective signals when the input signals are in high or low ranges, and the G tone curve and the B tone curve are identical.

Abstract: A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.

Abstract: An electronic endoscope system is provided that includes an RGB transformer, an R-signal amplifier, and a GB-signal amplifier. The RGB transformer transforms image signals to RGB signals. The R-signal amplifier changes the amplitude of the R signals of the RGB signals to a predetermined gain value. The GB-signal amplifier nonlinearly changes the amplitude of the G signals and B signals of the RGB signals.

Abstract: Disclosed herein is a semiconductor device comprising an array having a hierarchical bit line structure, global bit lines adjacent to each other, local bit lines corresponding to the global bit lines, hierarchical switches, precharge circuits precharging the global bit lines, precharge circuits precharging the local bit lines, and a control circuit. When performing a test of the array, precharge voltages for the global bit lines are set to potentials different from each other, and the control circuit controls the potentials to be applied to the local bit lines through the global bit lines and the hierarchical switches.

Abstract: An electronic endoscope signal-processing device is provided that includes a gradation compensation processor. The gradation compensation processor compensates for R, G, and B gradations by controlling R, G, and B tone curves defining relationship between input values and output values of each of the R, G, and B signals. The R tone curve is shaped so as to squash the output values of the R Signal when the R signal input values are in a relatively low range and to expand the output values when the input values are in a relatively high range.

Abstract: Disclosed herein is a semiconductor device comprising a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit line with turning the switch ON, so that the local bit line receives the precharge voltage through the global bit line and the switch, and after a lapse of a predetermined time, a precharge voltage is further supplied to the local bit line without an intervention of the global bit line and the switch.

Abstract: An edge-enhancement device for subjecting input image data to edge enhancement so as to generate output image data has an edge-component generator, a weighting processor, and an addition processor. The input image data is obtained from a frame image having a plurality of pixels, and the input image data contains luminance data. The edge-component generator generates an edge component of the input image data. The weighting processor applies a weight according to the value of the luminance data of each pixel to a calculated edge component of each pixel so as to generate a weighted edge component for each pixel. The addition processor adds the weighted edge component of each pixel to the input image data of the pixel so as to generate the output image data.

Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.

Abstract: The present invention provides a family of BAG-1 related proteins from humans (BAG-1L, BAG-1, BAG-2, BAG-3, BAG-4 and BAG-5), the invertebrate C. elegans (BAG-1, BAG-2) and the fission yeast S. pombe (BAG-1A, BAG-1B) and the nucleic acid molecules that encode them.