Abstract: A counter circuit includes counting stages of n bits where n is a natural number. The counter circuit also includes a logic decoding circuit for determining the inputs of the counting stages, a logic circuit for adjusting the number of simultaneous changes so that the number of simultaneous changes of the logic decoding circuit can be made uniform, and a logic circuit for adjusting the load capacitance of the counting stages so that the load capacitance can be made uniform. The counter circuit may also include a test logic circuit for creating a test wave form on the basis of the outputs from the logic circuits for adjusting the number of simultaneous changes and the logic circuits for adjusting the load capacitance. Accordingly, it is possible to detect a failure of the logic circuits for adjusting the number of simultaneous changes and the logic circuits for adjusting the load capacitance which does not effect the counting output.

Abstract: A carburetor and a fuel seeding system having the same including an air suction passageway through which air is fed, and a fuel feeding passageway which is disposed so as to be intersected to the air suction passageway and through which fuel is fed, the air suction passageway and the fuel feeding passageway being intercommunicated to each other. A roughened surface portion is formed on a wall surface of at least one of the air suction passageway and the fuel feeding passageway to generate turbulence in fluid flow and promote carburetion and granulation of the air-fuel mixture due to the turbulence. The tip portion of a jet needle serving as a part of the fuel feeding passageway may be provided with a substantially flat surface portion or a substantially conical surface portion having a vertical angle above 145 degrees.

Abstract: A counter circuit which incurs a uniform number of logic changes whether the clock signal is rising or falling is used in both a first counter circuit for measuring the reference signal for horizontal scanning period and a second counter circuit for measuring signals in the vertical blanking period. Since the number of logic changes of the flip-flops with respect to the clock signal is uniform, a driving circuit for a solid-state image sensor is realized in which noise in the vertical blanking period does not appear in the video period even if by using 1H delay line.