Patents by Inventor Shinichi Tomita
Shinichi Tomita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090230304Abstract: In a VP-SEM that uses gas multiplication induced within a low-vacuum sample chamber and uses a method of detecting a positive displacement current, a secondary electron detector for the VP-SEM that responds at high speed, which can acquire a TV-Scan rate image at a low cost while saving a space is provided. A secondary electron detector is formed by forming the electron supplying electrode and the detection electrode on the flexible thin film type substrate such as a polyimide film, etc., by an etching method. Thereby, the space can be saved while realizing low cost due to mass production. Further, the ion horizontally moving with respect to the surface of the secondary electron detector is detected and the ion moving in a vertical direction returned to the sample holder is not detected, making it possible to realize a high-speed response.Type: ApplicationFiled: March 3, 2009Publication date: September 17, 2009Inventors: Michio Hatano, Sukehiro Ito, Nagahide Ishida, Shinichi Tomita, Wataru Kotake
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Patent number: 7528049Abstract: A bonded SOI wafer is manufactured by performing bonding in a state where organics exist on a surface of an active layer wafer and/or on a surface of a supporting wafer and performing heat-treating for bonding reinforcement in a state where the organics are trapped at an interface between the active layer wafer and the supporting wafer to form crystal defects at an interface between the active layer wafer and an oxide film and/or at an interface between the supporting wafer and the oxide film. This allows a simple and inexpensive gettering source to be formed at the interface between an SOI layer and an insulating layer (oxide film). Also, the bonded SOI wafer of the present invention that is manufactured by this method can effectively remove heavy-metal impurities that may have a negative impact on the characteristics of the device and/or the withstand voltage characteristics of the oxide film.Type: GrantFiled: July 23, 2007Date of Patent: May 5, 2009Assignee: Sumco CorporationInventors: Yasunobu Ikeda, Shinichi Tomita, Hiroyuki Miyahara
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Publication number: 20090093106Abstract: This bonded SOI substrate includes: an SOI layer having a low density impurity layer in which dopants are present at low density and a high density impurity layer in which dopants are present at high density; a wafer for a support substrate which supports said SOI layer; and a buried insulating film, wherein said SOI layer and said wafer for a support substrate are bonded with said buried insulating film therebetween, and gettering sites are formed in said high density impurity layer.Type: ApplicationFiled: September 24, 2008Publication date: April 9, 2009Applicant: SUMCO CORPORATIONInventors: Shinichi TOMITA, Masahide Tsutsumi
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Patent number: 7511271Abstract: A scanning electron microscope includes an irradiation optical system for irradiating an electron beam to a sample; a sample holder for supporting the sample, arranged inside a sample chamber; at least one electric field supply electrode arranged around the sample holder; and an ion current detection electrode.Type: GrantFiled: September 21, 2005Date of Patent: March 31, 2009Assignee: Hitachi Science Systems, Ltd.Inventors: Michio Hatano, Sukehiro Ito, Shinichi Tomita, Junichi Katane
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Patent number: 7442992Abstract: This bonded SOI substrate includes: an SOI layer having a low density impurity layer in which dopants are present at low density and a high density impurity layer in which dopants are present at high density; a wafer for a support substrate which supports said SOI layer; and a buried insulating film, wherein said SOI layer and said wafer for a support substrate are bonded with said buried insulating film therebetween, and gettering sites are formed in said high density impurity layer.Type: GrantFiled: May 18, 2005Date of Patent: October 28, 2008Assignee: Sumco CorporationInventors: Shinichi Tomita, Masahide Tsutsumi
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Publication number: 20080132032Abstract: A method for manufacturing a silicon wafer is characterized by performing one or both of grinding and polishing to a thin discoid silicon wafer to give bowl-shaped warpage that is concave at a central part to a wafer surface. One main surface of the thin discoid silicon wafer is adsorbed and held, and one or both of grinding and polishing are performed to the other main surface to fabricate a convex wafer whose thickness is increased from a wafer outer periphery toward a wafer center or fabricate a concave wafer whose thickness is reduced from the wafer outer periphery toward the wafer center. Then, the other main surface is adsorbed and held to protrude the center or the periphery of the one main surface side based on elastic deformation. One or both of grinding and polishing are carried out with respect to the one main surface to flatten the main surface, and adsorption and holding are released to give bowl-shaped warpage that is concave at the central part to the other main surface or the one main surface.Type: ApplicationFiled: November 28, 2007Publication date: June 5, 2008Inventors: Shinichi Tomita, Masao Yoshimuta, Yasuyuki Hashimoto, Akira Nakashima
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Patent number: 7378332Abstract: Provided are a bonding substrate whose defective bonding portion in a peripheral region of an active layer has been removed by a polishing applied thereto after a surface grinding, a manufacturing method of the same substrate and wafer periphery pressing jigs. After the surface grinding, a periphery removing polishing is applied from an active layer wafer side of a bonding wafer so that a peripheral region of the active layer may be removed and a central region thereof may be left un-removed. Consequently, a periphery grinding and a periphery etching according to the prior art can be eliminated. Furthermore, an etch pit on a circumferential face of a wafer which could be caused by the periphery etching and a contamination or a scratching in an SOI layer which could be caused by a silicon oxide film left un-ground-off can be prevented, thereby achieving high yield and low cost.Type: GrantFiled: May 2, 2003Date of Patent: May 27, 2008Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Shinichi Tomita, Kouji Yoshimaru
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Publication number: 20080035843Abstract: In a scanning electron microscope, a reflection plate at ground potential is provided in a specimen chamber and backscattering electrons given off from a specimen impinge on the reflection plate to generate subsidiary electrons. An electric field supply electrode applied with a positive voltage of +100 to +500V is arranged in a gap defined by the reflection plate and a specimen stage. A first detection electrode is arranged to detect ion current attributable to backscattering electrons and a second detection electrode is arranged to detect current representative of coexistence of ion currents attributable to secondary electron and backscattering electron. The scanning electron microscope constructed as above can achieve simultaneous separation/detection of secondary electron and backscattering electron.Type: ApplicationFiled: June 26, 2007Publication date: February 14, 2008Inventors: Michio Hatano, Sukehiro Ito, Shinichi Tomita, Junichi Katane
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Publication number: 20080020541Abstract: A bonded SOI wafer is manufactured by performing bonding in a state where organics exist on a surface of an active layer wafer and/or on a surface of a supporting wafer and performing heat-treating for bonding reinforcement in a state where the organics are trapped at an interface between the active layer wafer and the supporting wafer to form crystal defects at an interface between the active layer wafer and an oxide film and/or at an interface between the supporting wafer and the oxide film. This allows a simple and inexpensive gettering source to be formed at the interface between an SOI layer and an insulating layer (oxide film). Also, the bonded SOI wafer of the present invention that is manufactured by this method can effectively remove heavy-metal impurities that may have a negative impact on the characteristics of the device and/or the withstand voltage characteristics of the oxide film.Type: ApplicationFiled: July 23, 2007Publication date: January 24, 2008Inventors: Yasunobu Ikeda, Shinichi Tomita, Hiroyuki Miyahara
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Publication number: 20070284542Abstract: A charged particle beam apparatus facilitating adjusting the beam center axis of a charged particle beam in a case where optical conditions are modified or in a case where the beam center axis of the charged particle beam is moved due to state variation of the apparatus. When the beam center axis of a primary charged particle beam is adjusted with a deflector (aligner), a processing step (1) for measuring the sensitivity of the aligner and a processing step (2) for detecting the deviation between the center of the primary charged particle beam and the center of the objective aperture are provided. The charged particle beam apparatus has means for determining the aligner set values, using the aligner sensitivity measured in the processing step (1) and the amount of deviation detected in the processing step (2), such that the primary charged particle beam passes through the center of the objective aperture and controlling the aligner using the aligner set values.Type: ApplicationFiled: March 8, 2007Publication date: December 13, 2007Inventors: Takeshi Ogashiwa, Mitsugu Sato, Atsushi Takane, Toshihide Agemura, Yuusuke Narita, Takeharu Shichiji, Shinichi Tomita, Sukehiro Ito, Junichi Katane
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Patent number: 7208058Abstract: An active layer wafer having a larger diameter is placed over a stationary supporting substrate wafer having a smaller diameter. A pusher plate is pressed against an orientation flat of the larger wafer to move the wafer substantially in the horizontal direction. In the course of the pressing operation, the pusher plate is also pressed against the orientation flat of the smaller wafer so as to move the two wafers together. Then, as a result of each of the cut sections for alignment of the wafer being pressed against an aligning plate, the larger wafer and the smaller wafer can be bonded to each other with their centerlines and orientation flats aligned with respect to each other.Type: GrantFiled: June 8, 2004Date of Patent: April 24, 2007Assignee: Sumitomo Mitsubishi Silicon CorporationInventor: Shinichi Tomita
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Publication number: 20060186337Abstract: A scanning electron microscope includes an irradiation optical system for irradiating an electron beam to a sample; a sample holder for supporting the sample, arranged inside a sample chamber; at least one electric field supply electrode arranged around the sample holder; and an ion current detection electrode.Type: ApplicationFiled: September 21, 2005Publication date: August 24, 2006Inventors: Michio Hatano, Sukehiro Ito, Shinichi Tomita, Junichi Katane
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Publication number: 20060055003Abstract: This bonded SOI substrate includes: an SOI layer having a low density impurity layer in which dopants are present at low density and a high density impurity layer in which dopants are present at high density; a wafer for a support substrate which supports said SOI layer; and a buried insulating film, wherein said SOI layer and said wafer for a support substrate are bonded with said buried insulating film therebetween, and gettering sites are formed in said high density impurity layer.Type: ApplicationFiled: May 18, 2005Publication date: March 16, 2006Applicant: SUMCO CORPORATIONInventors: Shinichi Tomita, Masahide Tsutsumi
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Publication number: 20050014347Abstract: Provided are a bonding substrate whose defective bonding portion in a peripheral region of an active layer has been removed by a polishing applied thereto after a surface grinding, a manufacturing method of the same substrate and wafer periphery pressing jigs. After the surface grinding, a periphery removing polishing is applied from an active layer wafer side of a bonding wafer so that a peripheral region of the active layer may be removed and a central region thereof may be left un-removed. Consequently, a periphery grinding and a periphery etching according to the prior art can be eliminated. Furthermore, an etch pit on a circumferential face of a wafer which could be caused by the periphery etching and a contamination or a scratching in an SOI layer which could be caused by a silicon oxide film left un-ground-off can be prevented, thereby achieving high yield and low cost.Type: ApplicationFiled: May 2, 2003Publication date: January 20, 2005Inventors: Shinichi Tomita, Kouji Yoshimaru
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Publication number: 20040246795Abstract: An active layer wafer having a larger diameter is placed over a stationary supporting substrate wafer having a smaller diameter. A pusher plate is pressed against an orientation flat of the larger wafer to move the wafer substantially in the horizontal direction. In the course of the pressing operation, the pusher plate is also pressed against the orientation flat of the smaller wafer so as to move the two wafers together. Then, as a result of each of the cut sections for alignment of the wafer being pressed against an aligning plate, the larger wafer and the smaller wafer can be bonded to each other with their centerlines and orientation flats aligned with respect to each other.Type: ApplicationFiled: June 8, 2004Publication date: December 9, 2004Inventor: Shinichi Tomita
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Publication number: 20040137697Abstract: A method and an apparatus for separating a composite substrate 1 by which the composite substrate 1 is warped to cause a crack and grow it in a separation region 6, a silicon substrate 2 constituting the composite substrate 1 is separated along the separation region 6, and the silicon substrate 2 is separated from the composite substrate 1 with ease.Type: ApplicationFiled: January 10, 2003Publication date: July 15, 2004Inventor: Shinichi Tomita
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Patent number: 6620285Abstract: A method for bonding substrates to tightly bond two overlaid substrates comprises the steps of: aligning the substrates, freely falling a second substrate onto a first substrate to overlay the first and second substrates; interposing an air layer between the joining surfaces of the first and second substrates, aligning the first and second substrates and holding the aligned first and second substrates; and pressing one point of the aligned two substrates. Thus, the bonded substrates which can be aligned accurately and free from occurrence of voids or the like can be obtained.Type: GrantFiled: October 10, 2001Date of Patent: September 16, 2003Assignee: Sumitomo Metal IndustriesInventors: Shinichi Tomita, Shuhei Tsuda, Yasunobu Ikeda
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Publication number: 20020040754Abstract: A method for bonding substrates to tightly bond two overlaid substrates comprises the steps of: aligning the substrates, freely falling a second substrate onto a first substrate to overlay the first and second substrates; interposing an air layer between the joining surfaces of the first and second substrates, aligning the first and second substrates and holding the aligned first and second substrates; and pressing one point of the aligned two substrates. Thus, the bonded substrates which can be aligned accurately and free from occurrence of voids or the like can be obtained.Type: ApplicationFiled: October 10, 2001Publication date: April 11, 2002Inventors: Shinichi Tomita, Shuhei Tsuda, Yasunobu Ikeda
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Patent number: 5246645Abstract: A method of controlling an injection molding machine in which change in the forward movement velocity of an injecting screw or change in the filling pressure is detected at the time of performing switching from the filling process to the packing process, commencement of the packing control is hastened if the change in the velocity or the pressure is reversed, while the commencement of the packing process is delayed if a determined level is not realized within a predetermined time from the commencement of the packing control. When the injection molding work is performed, switching from the filling process to the packing process can be easily performed at a proper time and therefore high quality products can be easily mass-produced.Type: GrantFiled: May 22, 1992Date of Patent: September 21, 1993Assignee: Ube Industries, Ltd.Inventors: Sainori Tagawa, Shinichi Tomita
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Patent number: 5170166Abstract: The invented auto-ranging device has a signal measuring A/D converter, a range-switching A/D converter of a faster processing speed, a range-switching amplifier with variable amplification capabilities, and a processing controller which utilizes the variable amplification factors to alter the output signals from the switching A/D converter to generate signals appropriate for a scale range of a multi-range measuring A/D converter.Type: GrantFiled: November 26, 1990Date of Patent: December 8, 1992Assignee: Fujikura Ltd.Inventors: Masao Tanaka, Shinichi Tomita, Yoshiharu Unami, Hiroyuki Kawasaki