Abstract: A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

Abstract: A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

Abstract: The synchronous circuit has: a phase comparator for comparing a feedback signal with an input reference signal to detect a phase difference and outputting a phase difference signal corresponding to the phase difference; a charge pump for outputting charge/discharge signals on the basis of the phase difference signal output from said phase comparator; a low-pass filter for changing a charge amount accumulated in a capacitor on the basis of the charge/discharge signals output from said charge pump and outputting control signals corresponding to the charge amount as differential signals; a voltage-controlled oscillator for changing an oscillation frequency of an output on the basis of the control signals output from said low-pass filter; a frequency divider for multiplying the output from said voltage-controlled oscillator and outputting the feedback signal; and fixing means arranged on an output side of said charge pump and operated, when the phase difference between the reference signal and the feedback signal

Abstract: A microprocessor incorporating a PLL circuit using a clock pulse having a relatively low frequency as an input clock signal of a reference frequency to form an oscillating pulse of a relatively high frequency by multiplying the input clock signal. In the microprocessor, the operation of the PLL circuit is stopped in the low-speed mode to supply the clock pulse of the relatively low frequency to the microprocessor as a system clock signal, and, in the high-speed mode, the PLL circuit is activated upon reception of an event requiring high-speed processing. Until the operation of the PLL circuit is stabilized and the request for high-speed processing comes, the above-mentioned clock pulse having the relatively low frequency is kept supplied continuously to the microprocessor as the system clock signal. This novel setup permits the high-speed switching of the microprocessor from the operating mode to the high-speed operating mode.

Abstract: A compiler incorporates obtained information for controlling the data-processor hardware, such as the position of the branch destination of a branch instruction and the used states of registers into object codes (NOP instruction) including a no-operation instruction code to post it to the data processor. The data processor is so constituted as to effectively use the data-processor resource not practically used by the no-operation instruction code and reflect the hardware control information included in the object code on data processing.

Abstract: A weather strip for an automobile comprising a trim portion securable to a flange of an automobile. The trim portion has a holding piece and a concave portion. The concave portion is disposed at a base portion of the holding piece and is in contact with an end of the flange. The concave portion is cooperable with the end of the flange to enable the trim portion to be slidably rotatable with respect to the end of the flange when being secured to the flange. An adhesive is provided at an inner surface of the holding piece for adhering the trim portion to the flange.

Abstract: A weatherstrip including a strip body provided with base. The base includes a surface to which the weatherstrip is fitted onto a vehicle body and a seal portion formed integrally with the base. An adhesive layer is applied on the fitting surface, for adhering the strip body to the vehicle body. A release liner is provided for protecting the adhesive layer until the weatherstrip is fitted. The release liner contains a synthetic resin non-woven fabric layer and a film layer laminated thereon, and has a high tensile strength.

Abstract: An aqueous coating composition comprising, as essential components, an aqueous polyurethane resin (A) obtained by reacting a diisocyanate and glycols containing a carboxylic acid group-containing glycol to prepare an urethane prepolymer, neutralizing the urethane prepolymer and subjecting the neutralized urethane prepolymer to chain extension with a hydrazine derivative, and an aqueous dispersion (B) of an acrylic copolymer whose constituent monomers contain carbonyl group-containing monomer or an amido group-containing monomer in an amount of at least 0.

Abstract: A process for producing an emulsion polymer composition which comprises (a) emulsion-polymerizing an ethylenically unsaturated monomer containing no amino group in the molecule in the presence of a water-insoluble epoxy resin to form an emulsion polymer as seed particles, and then (b) emulsion-polymerizing an ethylenically unsaturated monomer containing an amino group in the molecule and another ethylenically unsaturated monomer copolymerizable with it in the presence of the emulsion polymer formed in step (a); in which(1) the weight ratio of the ethylenically unsaturated monomer to the epoxy resin in step (a) is from 100:100 to 100:5,(2) the weight ratio of the amino group-containing ethylenically unsaturated monomer to the other ethylenically unsaturated monomer in step (b) is from 1:99 to 25:75,(3) the ethylenically unsaturated monomer in step (a) and/or (b) contains 1 to 10% by weight of an ethylenically unsaturated carboxylic acid,(4) the weight ratio of the ethylenically unsaturated monomer in step (a)