Patents by Inventor Shinichiro Matsumura

Shinichiro Matsumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11487428
    Abstract: A storage control apparatus, includes a memory; and a processor coupled to the memory and configured to: receive management information for managing data stored in a first storage device, generate, for each processing unit of the data, restoration information for restoring the management information, add the data to the restoration information by processing the data based on the management information on a second storage device, store, in the first storage device, the added restoration information, and reconstruct the management information on the second storage device based on the added restoration information when detecting an abnormality occurrence on the receiving the management information.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: November 1, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Shinichiro Matsumura
  • Publication number: 20210223957
    Abstract: A storage apparatus, includes a memory; and a processor coupled to the memory and configured to: receive management information for managing data stored in a first storage device, generate, for each processing unit of the data, restoration information for restoring the management information, add the data to the restoration information by processing the data based on the management information on a second storage device, store, in the first storage device, the added restoration information, and reconstruct the management information on the second storage device based on the added restoration information.
    Type: Application
    Filed: November 25, 2020
    Publication date: July 22, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Shinichiro Matsumura
  • Patent number: 10402108
    Abstract: Management information is provided to control a storage including storage-areas so that each storage-area includes a set of data-areas allocated from each storage-area and each set of data-areas has a data-area size that is a different integer multiple of an access unit of the storage. Logical address information stores information identifying a data-area into which target-data obtained by compressing data has been written, in association with a logical address of the data. Upon reception of the data and the logical address of the data, the apparatus identifies the management information corresponding to a data-area size greater than or equal to a size of the target-data, writes the target-data into an unused data-area of one of the sets of data-areas corresponding to the identified management information, and stores, in the logical address information, information identifying a physical address of the unused data-area in association with the logical address of the data.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 3, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Shinichiro Matsumura
  • Patent number: 10346070
    Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 9, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shinichiro Matsumura, Motohiro Sakai, Takahiro Ohyama, Takuro Kumabe, Akihito Kobayashi
  • Patent number: 10234929
    Abstract: A first control apparatus includes a first memory unit including a local cache, a first power supply that supplies electric power to the first memory unit, and a control unit. The control unit controls a write into a memory device by a write-back method, using the local cache. The control unit mirrors data of the local cache in a mirror cache of a second control apparatus. The control unit determines whether the mirror cache is included in a second memory unit that receives electric power from a second power supply of the second control apparatus, upon detecting an abnormal state of a battery for supplying electric power to the second memory unit in case of power outage of the second power supply. The second memory unit switches write control for the memory device to a write-through method, when the second memory unit includes the mirror cache.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, Satoshi Yazawa, Atsushi Igashira, Wataru Iizuka, Motohiro Sakai, Akihito Kobayashi, Shinichiro Matsumura, Kenji Kobayashi
  • Publication number: 20180210667
    Abstract: Management information is provided to control a storage including storage-areas so that each storage-area includes a set of data-areas allocated from each storage-area and each set of data-areas has a data-area size that is a different integer multiple of an access unit of the storage. Logical address information stores information identifying a data-area into which target-data obtained by compressing data has been written, in association with a logical address of the data. Upon reception of the data and the logical address of the data, the apparatus identifies the management information corresponding to a data-area size greater than or equal to a size of the target-data, writes the target-data into an unused data-area of one of the sets of data-areas corresponding to the identified management information, and stores, in the logical address information, information identifying a physical address of the unused data-area in association with the logical address of the data.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 26, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Shinichiro Matsumura
  • Patent number: 9904474
    Abstract: A control device includes a processor. The processor is configured to collect plural types of performance information regarding a first data unit. The processor is configured to determine, on basis of the collected plural types of performance information, whether to transfer the first data unit from a first storage device which is under control of a first controller to a second storage device which is positioned as higher than the first storage device. The processor is configured to transfer the first data unit from the first storage device to the second storage device depending on a result of the determination.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: February 27, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Takuro Kumabe, Akihito Kobayashi, Motohiro Sakai, Shinichiro Matsumura, Takahiro Ohyama
  • Patent number: 9734087
    Abstract: A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and performs LRU control with the use of the shared queue. The control unit also provides a local queue in the memory space of the shared cache memory. The control unit enqueues a CBE (management information) for a cache page used by a core in a process to the local queue. The control unit dequeues a plurality of CBEs from the local queue upon satisfaction of a predetermined condition, and enqueues the dequeued CBEs to the shared queue.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: August 15, 2017
    Inventors: Takuro Kumabe, Akihito Kobayashi, Motohiro Sakai, Shinichiro Matsumura, Takahiro Ohyama
  • Publication number: 20170147244
    Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.
    Type: Application
    Filed: October 6, 2016
    Publication date: May 25, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Shinichiro Matsumura, Motohiro Sakai, Takahiro Ohyama, Takuro Kumabe, Akihito Kobayashi
  • Publication number: 20170123699
    Abstract: A storage control device is one of a plurality of control devices each controlling different storage areas. The storage control device includes a memory and a processor coupled to the memory. The processor is configured to acquire an allocation request for allocating a storage area to a first virtual volume. The processor is configured to allocate a first storage area to the first virtual volume upon acquiring the allocation request. The first storage area is controlled by a first control device among the plurality of control devices. The first control device controls the first virtual volume.
    Type: Application
    Filed: October 20, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Takahiro Ohyama, Akihito Kobayashi, Motohiro Sakai, Shinichiro Matsumura, Takuro Kumabe
  • Patent number: 9632950
    Abstract: An apparatus includes a first cache memory, a second cache memory, and a processor coupled to the first cache memory and the second cache memory, and configured to store data in the second cache memory, the data being deleted from the first cache memory, store first data stored in a first address of the storage device, in the second cache memory, in case where the first address is included in first management information and is not included in second management information, according to a request for access to the first address of the storage device, the first management information including an address in the storage device of specific data stored in the storage device, and the second management information including an address in the storage device of data stored in both of the second cache memory and the storage device, and register the first address in the second management information.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 25, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shinichiro Matsumura, Akihito Kobayashi, Motohiro Sakai, Takahiro Ohyama, Takuro Kumabe
  • Publication number: 20160321175
    Abstract: A first control apparatus includes a first memory unit including a local cache, a first power supply that supplies electric power to the first memory unit, and a control unit. The control unit controls a write into a memory device by a write-back method, using the local cache. The control unit mirrors data of the local cache in a mirror cache of a second control apparatus. The control unit determines whether the mirror cache is included in a second memory unit that receives electric power from a second power supply of the second control apparatus, upon detecting an abnormal state of a battery for supplying electric power to the second memory unit in case of power outage of the second power supply. The second memory unit switches write control for the memory device to a write-through method, when the second memory unit includes the mirror cache.
    Type: Application
    Filed: March 23, 2016
    Publication date: November 3, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Hidefumi Kobayashi, SATOSHI YAZAWA, Atsushi IGASHIRA, Wataru Iizuka, Motohiro Sakai, Akihito Kobayashi, Shinichiro Matsumura, Kenji KOBAYASHI
  • Publication number: 20160085446
    Abstract: A control device includes a processor. The processor is configured to collect plural types of performance information regarding a first data unit. The processor is configured to determine, on basis of the collected plural types of performance information, whether to transfer the first data unit from a first storage device which is under control of a first controller to a second storage device which is positioned as higher than the first storage device. The processor is configured to transfer the first data unit from the first storage device to the second storage device depending on a result of the determination.
    Type: Application
    Filed: August 10, 2015
    Publication date: March 24, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Takuro Kumabe, Akihito Kobayashi, Motohiro Sakai, Shinichiro Matsumura, Takahiro Ohyama
  • Publication number: 20160062915
    Abstract: An apparatus includes a first cache memory, a second cache memory, and a processor coupled to the first cache memory and the second cache memory, and configured to store data in the second cache memory, the data being deleted from the first cache memory, store first data stored in a first address of the storage device, in the second cache memory, in case where the first address is included in first management information and is not included in second management information, according to a request for access to the first address of the storage device, the first management information including an address in the storage device of specific data stored in the storage device, and the second management information including an address in the storage device of data stored in both of the second cache memory and the storage device, and register the first address in the second management information.
    Type: Application
    Filed: June 29, 2015
    Publication date: March 3, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Shinichiro MATSUMURA, Akihito Kobayashi, Motohiro Sakai, Takahiro Ohyama, Takuro Kumabe
  • Publication number: 20150278114
    Abstract: A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and performs LRU control with the use of the shared queue. The control unit also provides a local queue in the memory space of the shared cache memory. The control unit enqueues a CBE (management information) for a cache page used by a core in a process to the local queue. The control unit dequeues a plurality of CBEs from the local queue upon satisfaction of a predetermined condition, and enqueues the dequeued CBEs to the shared queue.
    Type: Application
    Filed: March 3, 2015
    Publication date: October 1, 2015
    Inventors: Takuro Kumabe, Akihito Kobayashi, Motohiro Sakai, Shinichiro Matsumura, Takahiro Ohyama