Abstract: In a semiconductor device having a lateral transistor, a source wiring layer is disposed above at least a part of an interlayer insulating film. The interlayer insulating film is electrically connected to a source electrode and is extended toward a drain region to form a source field plate.

Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor element arranged on a predetermined surface side of the semiconductor substrate. The semiconductor element includes: a first region portion at which a first conductivity type semiconductor region is arranged on the surface side of the semiconductor substrate; a second region portion at a position separated from the first region portion; and a gate electrode arranged between the first region portion and the second region portion through an insulating film. In the first region portion, a first conductivity type semiconductor region is arranged. In the second region portion, a first conductivity type semiconductor region and a second conductivity type semiconductor region are alternately arranged.

Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor element arranged on a predetermined surface side of the semiconductor substrate. The semiconductor element includes: a first region portion at which a first conductivity type semiconductor region is arranged on the surface side of the semiconductor substrate; a second region portion at a position separated from the first region portion; and a gate electrode arranged between the first region portion and the second region portion through an insulating film. In the first region portion, a first conductivity type semiconductor region is arranged. In the second region portion, a first conductivity type semiconductor region and a second conductivity type semiconductor region are alternately arranged.

Abstract: In the interior of a semiconductor substrate having a main surface, a first p? epitaxial region is formed, a second p? epitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An n+ buried region is formed between the first p? epitaxial region and the second p? epitaxial region in order to electrically isolate the regions. A p+ buried region having a p-type impurity concentration higher than that of the second p? epitaxial region is formed between the n+ buried region and the second p? epitaxial region. The p+ buried region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.

Abstract: In the interior of a semiconductor substrate having a main surface, a first p? epitaxial region is formed, a second p? epitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An n+ buried region is formed between the first p? epitaxial region and the second p? epitaxial region in order to electrically isolate the regions. A p+ buried region having a p-type impurity concentration higher than that of the second p? epitaxial region is formed between the n+ buried region and the second p? epitaxial region. The p+ buried region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

Abstract: There is provided a semiconductor device in which the degradation of electric characteristics can be inhibited. A semiconductor substrate has a main surface, and a trench in the main surface. A buried insulating film is buried in the trench. The trench has one wall surface and the other wall surface which oppose each other. A gate electrode layer is located over at least the buried insulating film. The trench has angular portions which are located between the main surface of at least either one of the one wall surface and the other wall and a bottom portion of the trench.

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

Abstract: Provided is a semiconductor device which scarcely malfunctions even when the device is used as a high-side element, and can keep a high breakdown voltage. In a semiconductor substrate having a main surface, a first p? epitaxial region is formed. At the main surface side of the first p? epitaxial region, a second p? epitaxial region is formed. At the main surface side of the second p? epitaxial region, an n-type drift region and a p-type body region are formed. Between the first and second p? epitaxial regions, an n+ buried region having a floating potential is formed to isolate these regions electrically from each other. Between n+ buried region and the second p? epitaxial region, a p+ buried region is formed which has a higher p-type impurity concentration than the second p? epitaxial region.

Abstract: There is provided a semiconductor device in which the degradation of electric characteristics can be inhibited. A semiconductor substrate has a main surface, and a trench in the main surface. A buried insulating film is buried in the trench. The trench has one wall surface and the other wall surface which oppose each other. A gate electrode layer is located over at least the buried insulating film. The trench has angular portions which are located between the main surface of at least either one of the one wall surface and the other wall and a bottom portion of the trench.

Abstract: The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n? type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

Abstract: The invention provides a semiconductor device capable of protecting a low-concentration implantation region from contamination, and a method for manufacturing the same. A photoresist is formed on a TEOS film which is formed all over a substrate, and removed by photo engraving so as to be partially left. This photo resist is of a positive or negative type opposite to a type of a photoresist used for formation of a p-offset region and a diffusion region. Then, the TEOS film is etched back except for a portion just under the photoresist. Thereby, a contamination protective film is formed just under the photoresist, and a side wall is formed on a side face of a gate electrode.

Abstract: The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n? type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.