Abstract: An object of the present invention is to provide a trench gate type IGBT achieving both retention of withstand voltage and lowering of ON-state voltage and to provide a method for manufacturing the trench gate type IGBT. The IGBT according to the present invention is an SJ-RC-IGBT which includes a drift layer having super junction structure, and includes an IGBT area and an FWD area on the rear surface. In the IGBT according to the present invention, a first drift layer has an impurity concentration of 1×1015 atms/cm3 or higher and lower than 2×1016 atms/cm3, and a thickness of 10 ?m or larger and smaller than 50 ?m; and that a buffer layer has an impurity concentration of 1×1015 atms/cm3 or higher and lower than 2×1016 atms/cm3, and a thickness of 2 ?m or larger and smaller than 15 ?m.

Abstract: An object of the present invention is to provide a trench gate type IGBT achieving both retention of withstand voltage and lowering of ON-state voltage and to provide a method for manufacturing the trench gate type IGBT. The IGBT according to the present invention is an SJ-RC-IGBT which includes a drift layer having super junction structure, and includes an IGBT area and an FWD area on the rear surface. In the IGBT according to the present invention, a first drift layer has an impurity concentration of 1×1015 atms/cm3 or higher and lower than 2×1016 atms/cm3, and a thickness of 10 ?m or larger and smaller than 50 ?m; and that a buffer layer has an impurity concentration of 1×1015 atms/cm3 or higher and lower than 2×1016 atms/cm3, and a thickness of 2 ?m or larger and smaller than 15 ?m.

Abstract: A trench gate IGBT designed to reduce on-state voltage while maintaining the withstand voltage, including a first drift layer formed on a first main surface of a buffer layer, a second drift layer of the first conductivity type formed on said first drift layer, a base layer of a second conductivity type formed on the second drift layer, an emitter layer of the first conductivity type selectively formed in the surface of the base layer, and a gate electrode buried from the surface of the emitter layer through into the second drift layer with a gate insulating film therebetween, wherein said first drift layer has a structure in which a first layer of the first conductivity type and a second layer of the second conductivity type are repeated in a horizontal direction.

Abstract: A trench gate IGBT designed to reduce on-state voltage while maintaining the withstand voltage, including a first drift layer formed on a first main surface of a buffer layer, a second drift layer of the first conductivity type formed on said first drift layer, a base layer of a second conductivity type formed on the second drift layer, an emitter layer of the first conductivity type selectively formed in the surface of the base layer, and a gate electrode buried from the surface of the emitter layer through into the second drift layer with a gate insulating film therebetween, wherein said first drift layer has a structure in which a first layer of the first conductivity type and a second layer of the second conductivity type are repeated in a horizontal direction.

Abstract: A carrier storage layer is located in a region of a predetermined depth from a surface of an N? substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N? substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N? substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.

Abstract: An insulated gate bipolar transistor includes a first main electrode on a first main surface and in contact with a base region of an insulated gate transistor at the first main surface, a first semiconductor layer of a first conductivity type on a second main surface, a second semiconductor layer of a second conductivity type on the second main surface and vertically aligned with a region of the first main electrode in contact with the base region, and a second main electrode formed on the first and second semiconductor layers. An interface between the second main electrode and each of the first and second semiconductor layers is parallel to the first main surface, a distance between the first main surface and the interface is equal to 200 ?m or smaller, and a thickness of each of the first and second semiconductor layers is equal to 2 ?m or smaller.

Abstract: A p-type region is provided on a first n-type region. A second n-type region is provided on the p-type region, spaced apart from the first n-type region by the p-type region. A gate electrode serves to form an n-channel between the first and second n-type regions. A first electrode is electrically connected to each of the p-type region and the second n-type region. A second electrode is provided on the first n-type region such that it is spaced apart from the p-type region by the first n-type region and at least a part thereof is in contact with the first n-type region. The second electrode is made of any of metal and alloy and serves to inject holes into the first n-type region.

Abstract: An insulated gate bipolar transistor includes a first main electrode on a first main surface and in contact with a base region of an insulated gate transistor at the first main surface, a first semiconductor layer of a first conductivity type on a second main surface, a second semiconductor layer of a second conductivity type on the second main surface and vertically aligned with a region of the first main electrode in contact with the base region, and a second main electrode formed on the first and second semiconductor layers. An interface between the second main electrode and each of the first and second semiconductor layers is parallel to the first main surface, a distance between the first main surface and the interface is equal to 200 ?m or smaller, and a thickness of each of the first and second semiconductor layers is equal to 2 ?m or smaller.

Abstract: A carrier storage layer is located in a region of a predetermined depth from a surface of an N? substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N? substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N? substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.

Abstract: To provide a reverse conducting semiconductor device in which an insulated gate bipolar transistor and a free wheeling diode excellent in recovery characteristic are monolithically formed on a substrate, the free wheeling diode including; a second conductive type base layer to constitute the insulated gate bipolar transistor; a first conductive type base layer for constituting the insulated gate bipolar transistor, an anode electrode which is an emitter electrode covering a first conductive type emitter layer and the second conductive type base layer, a cathode electrode which is a collector electrode covering the first conductive type base layer and a second conductive type collector layer formed on the part of the first conductive type base layer, wherein a short lifetime region is formed on a part of the first conductive type base layer.

Abstract: It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N?-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N?-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N?-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N?-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N?-type silicon substrate (1).

Abstract: To provide a reverse conducting semiconductor device in which an insulated gate bipolar transistor and a free wheeling diode excellent in recovery characteristic are monolithically formed on a substrate, the free wheeling diode including; a second conductive type base layer to constitute the insulated gate bipolar transistor; a first conductive type base layer for constituting the insulated gate bipolar transistor, an anode electrode which is an emitter electrode covering a first conductive type emitter layer and the second conductive type base layer, a cathode electrode which is a collector electrode covering the first conductive type base layer and a second conductive type collector layer formed on the part of the first conductive type base layer, wherein a short lifetime region is formed on a part of the first conductive type base layer.

Abstract: It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N?-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N?-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N?-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N?-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N?-type silicon substrate (1).

Abstract: It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N?-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N?-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N?-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N?-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N?-type silicon substrate (1).

Abstract: It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N?-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N?-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N?-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N?-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N?-type silicon substrate (1).

Abstract: In an IGBT with a built-in freewheeling diode, a thickness (D) of a polished wafer is equal to 200 ?m or smaller, and each of respective thicknesses (T8) and (T9) of an N+-type cathode layer (8) and a P+-type collector layer (9) is equal to 2 ?m or smaller. Further, a total width of the N+-type cathode layer (8) and the P+-type collector layer (9) which extends along a width direction (X) is in a range from 50 ?m to 200 ?m. In this case, an interface (IF2) between a collector electrode (10) and the P+-type collector layer (9) occupies 30-80% of an interface (IF) between the collector electrode (10) and the P+-type collector layer (9) plus the N+-type cathode layer (8).

Abstract: A semiconductor device and a manufacturing method therefor are provided, the semiconductor device having a good reverse recovery characteristic, and having no reduction in breakdown voltage because no defect occurs in the upper main surface of a Si substrate even when wires are bonded onto an anode electrode. A semiconductor device includes a Si substrate including an N+ cathode layer and an N? layer. An impurity such as platinum whose barrier height is less than that of silicon is introduced into upper regions of the N? layer where P anode layers are not formed, thereby forming Schottky junction regions. A barrier metal is formed between the Si substrate and an anode electrode.

Abstract: A semiconductor device and a manufacturing method therefor are provided, the semiconductor device having a good reverse recovery characteristic, and having no reduction in breakdown voltage because no defect occurs in the upper main surface of a Si substrate even when wires are bonded onto an anode electrode. A semiconductor device comprises a Si substrate including an N+ cathode layer (101) and an N− layer (102). An impurity such as platinum whose barrier height is less than that of silicon is introduced into upper regions of the N− layer (102) where P anode layers (103) are not formed, thereby forming Schottky junction regions (104). A barrier metal (105) is formed between the Si substrate and an anode electrode (106).

Abstract: It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N−-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N−-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N−-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N−-type silicon substrate (1).

Abstract: An anode electrode metal layer composed of aluminum is formed in a region on the inner side than an anode layer formed on a main surface of a semiconductor substrate. Thus, an impurity diffusion region from the innermost circumferential surface of said surface of field limiting innermost circumferential layer to the outermost circumferential surface of the anode electrode metal layer may be used as an electrical resistance. As a result, the hole density distributed from the bottom side of the field limiting innermost circumferential layer to a cathode layer when forward bias is applied may be reduced. As a result, when a reverse bias is applied, locally great recovery current passed from a cathode layer to the bottom of field limiting innermost circumferential layer may be restrained. Therefore, a diode capable of preventing destruction of a field limiting innermost circumferential layer when a reverse bias is applied may be provided.