Patents by Inventor Shinji Fujii
Shinji Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7683402Abstract: Semiconductor devices whose current characteristics can be prevented from varying even if a phase shift mask is used for patterning gate electrodes of MISFETs, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, there is provided a semiconductor device comprising a first transistor including a first gate electrode provided above a semiconductor substrate, and a first source and a first drain provided in the semiconductor substrate, a second transistor arranged to be adjacent to the first transistor, and including a second gate electrode provided above the semiconductor substrate in parallel with the first gate electrode, and a second source and a second drain provided in the semiconductor substrate, and a third gate electrode provided between the first transistor and the second transistor and in parallel with the first and second gate electrodes.Type: GrantFiled: September 20, 2007Date of Patent: March 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Fujii, Kouichirou Inoue, Naoto Higuchi, Taisei Suzuki
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Publication number: 20100009268Abstract: The present invention intends to provide a lithium primary battery excellent in large-current discharge characteristics in a low temperature environment without sacrificing the high-temperature storage characteristics. The present invention relates to a lithium primary battery including a positive electrode including a fluoride as a positive electrode active material, a negative electrode including metallic lithium or a lithium alloy as a negative electrode active material, a separator interposed between the positive electrode and the negative electrode, and an electrolyte. The positive electrode further includes a metal oxide being capable of absorbing and desorbing lithium ions, having a spinel structure, and having a discharge potential versus lithium lower than that of the fluoride.Type: ApplicationFiled: October 18, 2006Publication date: January 14, 2010Applicant: PANASONIC CORPORATIONInventors: Tohru Hitomi, Susumu Yamanaka, Shinji Fujii, Kenichi Takata, Kenichi Morigaki
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Publication number: 20090123844Abstract: A lithium primary battery including a positive electrode, a negative electrode, an organic electrolyte, and a separator interposed between the positive electrode and the negative electrode: the negative electrode including a negative electrode active material; the negative electrode active material being at least one selected from the group consisting of lithium metal and a lithium alloy; at least a surface layer portion of the negative electrode including a composite of amorphous carbon material and the negative electrode active material; and the surface layer portion facing the positive electrode with the separator interposed therebetween.Type: ApplicationFiled: October 7, 2005Publication date: May 14, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kenichi Morigaki, Susumu Yamanaka, Tohru Hitomi, Shinji Fujii, Toshihiko Ikehata
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Publication number: 20090025131Abstract: Provided are a toilet seat device saving energy and accurately stabilizing the temperature of a seating section at a predetermined level in a short time, and a toilet apparatus having the same. A control section adjusts the temperature of a toilet seat section to 18° C. when a heating function is turned on, and during a standby period D1, the control section performs low electric power drive of a lamp heater provided at the toilet seat section. The control section starts 600 W drive of the lamp heater at time t1 after the control section detects user's entry into a room, and the control section maintains the 600 W drive during an inrush current reduction period D2. The control section starts 1200 W drive of the lamp heater at time t2 and maintains the 1200 W drive during a first temperature rise period D3.Type: ApplicationFiled: June 26, 2006Publication date: January 29, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yuuji Yamamoto, Hidetoshi Amaya, Shinji Fujii, Noboru Okui, Hiroshi Nagasato, Kenji Yoshinaga, Masahiro Takiguchi, Kazuya Kondoh, Eiichi Tanaka, Mitsuhiro Fukuda
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Publication number: 20080290454Abstract: A semiconductor integrated circuit device includes a plurality of metal wirings which are separated from one another with respective interlayer insulating films; at least one interlayer conductor for connecting adjacent ones of the metal wirings via the corresponding one of the interlayer insulating films; at least one functional element formed above a semiconductor substrate and between adjacent ones of the interlayer insulating films; and at least one dummy metal portion which is formed above and/or below the functional element via at least one of the interlayer insulating films so as to be located inside the at least one interlayer conductor.Type: ApplicationFiled: February 4, 2008Publication date: November 27, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Shinji Fujii
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Patent number: 7436007Abstract: A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns are arranged to be spaced from each other, and are arranged so as to be adjacent to the first and second patterns. The fifth pattern is arranged between the first and second grid lines to interconnect the first to fourth patterns. A dimension of the fifth pattern in a direction of extension of a plurality of grid lines is set to be smaller than a dimension obtained by adding dimensions of the first and second patterns in the direction of extension of the grid lines to an interval of the both patterns, and a dimension obtained by adding dimensions of the third and fourth patterns to an interval of the both patterns.Type: GrantFiled: July 5, 2006Date of Patent: October 14, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Fujii, Toshiki Morimoto
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Publication number: 20080073728Abstract: Semiconductor devices whose current characteristics can be prevented from varying even if a phase shift mask is used for patterning gate electrodes of MISFETs, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, there is provided a semiconductor device comprising a first transistor including a first gate electrode provided above a semiconductor substrate, and a first source and a first drain provided in the semiconductor substrate, a second transistor arranged to be adjacent to the first transistor, and including a second gate electrode provided above the semiconductor substrate in parallel with the first gate electrode, and a second source and a second drain provided in the semiconductor substrate, and a third gate electrode provided between the first transistor and the second transistor and in parallel with the first and second gate electrodes.Type: ApplicationFiled: September 20, 2007Publication date: March 27, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinji Fujii, Kouichirou Inoue, Naoto Higuchi, Taisei Suzuki
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Publication number: 20070273028Abstract: A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.Type: ApplicationFiled: May 24, 2007Publication date: November 29, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Nobuhiko Kurata, Kouichirou Inoue, Shinji Fujii, Muneaki Maeno
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Patent number: 7165560Abstract: In order to reliably remove, by wet etching, a compound containing a metal and silicon, e.g., a silicate (101a) containing hafnium metal, the silicate (101a) is oxidized and then the oxidized silicate (101a) is wet-etched.Type: GrantFiled: June 5, 2003Date of Patent: January 23, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Shinji Fujii
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Publication number: 20070007549Abstract: A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns are arranged to be spaced from each other, and are arranged so as to be adjacent to the first and second patterns. The fifth pattern is arranged between the first and second grid lines to interconnect the first to fourth patterns. A dimension of the fifth pattern in a direction of extension of a plurality of grid lines is set to be smaller than a dimension obtained by adding dimensions of the first and second patterns in the direction of extension of the grid lines to an interval of the both patterns, and a dimension obtained by adding dimensions of the third and fourth patterns to an interval of the both patterns.Type: ApplicationFiled: July 5, 2006Publication date: January 11, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinji Fujii, Toshiki Morimoto
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Patent number: 6989583Abstract: A semiconductor device containing a multi-layered wiring structure formed on a semiconductor substrate, the structure including at least two wiring layers formed in an interlayer insulation layer, and each of the wiring layers including a metal wiring made of one of Cu and a Cu alloy, wherein the multi-layered wiring structure comprises a lower wiring layer formed under the interlayer insulation layer, a via buried in the interlayer insulation layer to connect an upper wiring layer and the lower wiring layer, and a dummy via buried in the interlayer insulation layer, the dummy via being not connected to the upper wiring layer.Type: GrantFiled: February 23, 2004Date of Patent: January 24, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Shinji Fujii
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Publication number: 20060009039Abstract: In order to reliably remove, by wet etching, a compound containing a metal and silicon, e.g., a silicate (101a) containing hafnium metal, the silicate (101a) is oxidized and then the oxidized silicate (101a) is wet-etched.Type: ApplicationFiled: August 15, 2005Publication date: January 12, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Shinji Fujii
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Patent number: 6915498Abstract: A semiconductor device includes a plurality of circuits, provided on a semiconductor substrate, each having a plurality of wiring layers. The plurality of circuits are designed using a common design core to which a plurality of wiring data are allocated.Type: GrantFiled: July 9, 2002Date of Patent: July 5, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Hashiba, Toshikazu Sei, Yukinori Uchino, Shinji Fujii
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Publication number: 20050029230Abstract: In order to reliably remove, by wet etching, a compound containing a metal and silicon, e.g., a silicate (101a) containing hafnium metal, the silicate (101a) is oxidized and then the oxidized silicate (101a) is wet-etched.Type: ApplicationFiled: June 5, 2003Publication date: February 10, 2005Inventor: Shinji Fujii
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Publication number: 20040222531Abstract: A semiconductor device containing a multi-layered wiring structure formed on a semiconductor substrate, the structure including at least two wiring layers formed in an interlayer insulation layer, and each of the wiring layers including a metal wiring made of one of Cu and a Cu alloy, wherein the multi-layered wiring structure comprises a lower wiring layer formed under the interlayer insulation layer, a via buried in the interlayer insulation layer to connect an upper wiring layer and the lower wiring layer, and a dummy via buried in the interlayer insulation layer, the dummy via being not connected to the upper wiring layer.Type: ApplicationFiled: February 23, 2004Publication date: November 11, 2004Inventor: Shinji Fujii
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Publication number: 20030015773Abstract: A semiconductor device includes a plurality of circuits, provided on a semiconductor substrate, each having a plurality of wiring layers. The plurality of circuits are designed using a common design core to which a plurality of wiring data are allocated.Type: ApplicationFiled: July 9, 2002Publication date: January 23, 2003Inventors: Yoshiaki Hashiba, Toshikazu Sei, Yukinori Uchino, Shinji Fujii
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Patent number: 5406135Abstract: A differential current source circuit includes three P-channel MOSFETs and two N-channel MOSFETs. Each source of first and second P-channel MOSFETs is connected to a power supply, and a bias voltage is applied to each gate of the MOSFETs. A current path of the first N-channel MOSFET is connected between a drain of the first P-channel MOSFET and a ground. A current path of the third P-channel MOSFET is connected between a drain of the second P-channel MOSFET and a current output terminal. A gate of the third P-channel MOSFET is connected to the drain of the first P-channel MOSFET. One end of a current path of the second N-channel MOSFET is connected to a connecting point of the first P-channel and first N-channel MOSFETs, and the other end is connected to a connecting point of the second P-channel and third P-channel MOSFETs. A digital signal is applied to a gate of the second N-channel MOSFET.Type: GrantFiled: November 24, 1993Date of Patent: April 11, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiko Kasai, Kenji Matsuo, Shinji Fujii, Yasukazu Noine
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Patent number: 5369318Abstract: The output terminal of an ECL circuit is directly connected to the input terminal of a CMOS output circuit. The CMOS output circuit has a transistor which sets the threshold voltage of the CMOS output circuit nearly midway between ECL logic levels. A first reference voltage generating circuit has substantially the same arrangement as the CMOS output circuit and outputs a potential midway between CMOS logic levels as a first reference voltage Vref1. The first reference voltage Vref1 is made variable. A second reference voltage generating circuit has substantially the same arrangement as the ECL circuit and outputs a potential which is midway between the ECL logic levels as a second reference voltage Vref2. A comparator makes a comparison between the first and second reference voltages Vref1 and Vref2 and controls the first reference voltage generating circuit and the CMOS output circuit so that the first and second reference voltages Vref1 and Vref2 may become equal to each other.Type: GrantFiled: June 23, 1993Date of Patent: November 29, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Tadahiro Kuroda, Shinji Fujii, Masahiro Kimura, Kazuhiko Kasai
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Patent number: 5268872Abstract: The gate of a first P-channel transistor of a first comparator is supplied with an input signal, and the gate of a second P-channel transistor of the first comparator is supplied with a reference voltage. An output terminal of the first comparator is connected to an output circuit and the gates of first and second P-channel transistors of a second comparator are supplied with the reference voltage. The second comparator outputs a voltage equal to a stand-by time output voltage of the first comparator and the output voltage from the second comparator is supplied to the non-inversion input terminal of a third comparator which is connected to a voltage generating circuit. The voltage generating circuit has substantially the same dimension ratio as the output circuit and generates a voltage equal to the threshold voltage of the output circuit.Type: GrantFiled: September 27, 1991Date of Patent: December 7, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Fujii, Tadahiro Kuroda, Kenji Matsuo, Ayako Hirata, Kazuhiko Kasai, Toshiyuki Fukunaga, Masahiro Kimura
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Patent number: 5235218Abstract: This invention discloses a switching constant current source circuit including a first current path for supplying a constant current, a first MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a second current path, and a gate of which is applied with a digital signal corresponding to a logical amplitude, a second MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a third current path, and which performs a switching operation complementary with the first MOS transistor, and level conversion means for fetching a change in voltage in the first current path caused by a change in current flowing through the first current path according to an operation of the first MOS transistor in response to the digital signal, and alternately applying a first level for disabling the second MOS transistor, which operates complementarType: GrantFiled: November 14, 1991Date of Patent: August 10, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Matsuo, Shinji Fujii, Yasukazu Noine, Kazuhiko Kasai