Abstract: The present invention provides a product with an operation display panel incorporated therein, which naturally harmonizes with the environment to not create visual noise for a user and allow the user to operate the operation display panel intuitively while feeling a natural material. A thin layer, made of a natural wood, natural fiber, natural leather, or natural stone, or a resin, synthetic fiber, synthetic leather or artificial stone created by imitating the appearance and touch of a natural material, is provided on the peripheral surface of a housing so that the thin layer covers at least the entire front surface of a display panel. A touch sensor incorporated comes in contact with the front surface of the panel. The thickness of the thin layer and the luminance of the panel are designed to allow the user to view the content displayed on the panel.

Abstract: The present invention provides a product with an operation display panel incorporated therein, which naturally harmonizes with the environment to not create visual noise for a user and allow the user to operate the operation display panel intuitively while feeling a natural material. A thin layer, made of a natural wood, natural fiber, natural leather, or natural stone, or a resin, synthetic fiber, synthetic leather or artificial stone created by imitating the appearance and touch of a natural material, is provided on the peripheral surface of a housing so that the thin layer covers at least the entire front surface of a display panel. A touch sensor incorporated comes in contact with the front surface of the panel. The thickness of the thin layer and the luminance of the panel are designed to allow the user to view the content displayed on the panel.

Abstract: The present invention provides a product with an operation display panel incorporated therein, which naturally harmonizes with the environment to not create visual noise for a user and allow the user to operate the operation display panel intuitively while feeling a natural material. A thin layer, made of a natural wood, natural fiber, natural leather, or natural stone, or a resin, synthetic fiber, synthetic leather or artificial stone created by imitating the appearance and touch of a natural material, is provided on the peripheral surface of a housing so that the thin layer covers at least the entire front surface of a display panel. A touch sensor incorporated comes in contact with the front surface of the panel. The thickness of the thin layer and the luminance of the panel are designed to allow the user to view the content displayed on the panel.

Abstract: A solid-state image pickup apparatus includes one or a plurality of photoelectric converting sections for photoelectric converting incident light into a signal charge on a semiconductor substrate, and a vertical charge-transferring section for charge-transferring the signal charge photoelectric converted at the photoelectric converting section, in which the vertical charge-transferring section is located under the photoelectric converting section on the side of the semiconductor substrate.

Abstract: A memory cell in a semiconductor memory device comprises a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element and the variable resistor element are placed one over the other along a direction in which the first electrode, the variable resistor body, and the second electrode of the variable resistor element are layered, and one of the first electrode and the second electrode of the variable resistor element is connected to one electrode of the transistor element.

Abstract: A semiconductor memory device comprises an array of memory cells each comprising a variable resistance element and a cell access transistor, and a voltage supplying means for applying the first voltage between the bit and source lines connected to the selected memory cell, the third voltage to the word line to apply the first write voltage between the two ports of the variable resistance element for shifting the resistance from the first state to the second state, and the second voltage opposite in polarity to the first voltage between the bit and source lines, the third voltage to the word line to apply the second write voltage opposite in polarity to and different in the absolute value from the first write voltage between the two ports for shifting the resistance from the second state to the first state, the voltage supplying means comprising an n-channel MOSFET and a p-channel MOSFET.

Abstract: A semiconductor memory device comprises a array of memory cells arranged in a matrix, each memory cell connected to one end of a variable resistor element where the electric resistance is shifted from the first state to the second state by applying the first writing voltage and from the second state to the first state by applying the second writing voltage, and the source or drain of the selecting transistor. The second writing time for the second writing action of shifting the electric resistance of the variable resistor element from the second state to the first state is longer than the first writing time of shifting the same reversely. The second number of the memory cells subjected to the second writing action at once is greater than the first memory cell number subjected to the first writing action at once, and at least the second number is two or more.

Abstract: The possibility of the loss of information stored in a memory cell which is caused by repeating the reading action on the same memory cell comprising a variable resistance element and a select transistor can significantly be reduced. A voltage applying circuit for selecting one or more of the memory cells from a memory cell array and applying voltages to the word lines, bit lines, and source lines for programming, erasing, and reading information applies a voltage between the bit line and the source line connected to the selected memory cell so that the voltage applied between the two ports of the variable resistance element in the selected memory cell during the reading action is equal in the polarity to one of the voltages applied between the two ports of the variable resistance element for the programming action and the erasing action respectively whichever is greater in the absolute value.

Abstract: A semiconductor device, which is characterized by that two or more island-shaped semiconductor layers including first and second island-shaped semiconductor layers are formed on the same substrate, at least the first island-shaped semiconductor layer has steps in its side wall so that sectional area of a cross section parallel to the surface of the substrate varies stepwise with respect to height in the vertical direction, the second island-shaped semiconductor layer is different from the first island-shaped semiconductor layer with respect to the presence/absence of a step in the side wall or the number of steps, and each of the first and second island-shaped semiconductor layers provides an element on a stair part of the side wall divided by the steps or on the side wall having no steps.

Abstract: A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a part

Abstract: A semiconductor memory device comprises an array of memory cells each comprising a variable resistance element and a cell access transistor, and a voltage supplying means for applying the first voltage between the bit and source lines connected to the selected memory cell, the third voltage to the word line to apply the first write voltage between the two ports of the variable resistance element for shifting the resistance from the first state to the second state, and the second voltage opposite in polarity to the first voltage between the bit and source lines, the third voltage to the word line to apply the second write voltage opposite in polarity to and different in the absolute value from the first write voltage between the two ports for shifting the resistance from the second state to the first state, the voltage supplying means comprising an n-channel MOSFET and a p-channel MOSFET.

Abstract: The possibility of the loss of information stored in a memory cell which is caused by repeating the reading action on the same memory cell comprising a variable resistance element and a select transistor can significantly be reduced. A voltage applying circuit for selecting one or more of the memory cells from a memory cell array and applying voltages to the word lines, bit lines, and source lines for programming, erasing, and reading information applies a voltage between the bit line and the source line connected to the selected memory cell so that the voltage applied between the two ports of the variable resistance element in the selected memory cell during the reading action is equal in the polarity to one of the voltages applied between the two ports of the variable resistance element for the programming action and the erasing action respectively whichever is greater in the absolute value.

Abstract: The present invention provides a semiconductor memory device having one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, wherein each of the memory cells is formed of a charge storage layer, a control gate and an impurity diffusion layer of a second conductivity type which is formed in a portion of the protruding semiconductor layer and the plurality of memory cells is aligned to at least a predetermined direction, and the control gates of the plurality of memory cells is aligned to the predetermined direction are placed so as to be separated from each other.

Abstract: A semiconductor memory device comprises a array of memory cells arranged in a matrix, each memory cell connected to one end of a variable resistor element where the electric resistance is shifted from the first state to the second state by applying the first writing voltage and from the second state to the first state by applying the second writing voltage, and the source or drain of the selecting transistor. The second writing time for the second writing action of shifting the electric resistance of the variable resistor element from the second state to the first state is longer than the first writing time of shifting the same reversely. The second number of the memory cells subjected to the second writing action at once is greater than the first memory cell number subjected to the first writing action at once, and at least the second number is two or more.

Abstract: A semiconductor device, which is characterized by that two or more island-shaped semiconductor layers including first and second island-shaped semiconductor layers are formed on the same substrate, at least the first island-shaped semiconductor layer has steps in its side wall so that sectional area of a cross section parallel to the surface of the substrate varies stepwise with respect to height in the vertical direction, the second island-shaped semiconductor layer is different from the first island-shaped semiconductor layer with respect to the presence/absence of a step in the side wall or the number of steps, and each of the first and second island-shaped semiconductor layers provides an element on a stair part of the side wall divided by the steps or on the side wall having no steps.

Abstract: The present invention provides a semiconductor memory device including: a semiconductor substrate of a first conductivity type; and a memory cell including: (i) a columnar semiconductor portion formed on the substrate, (ii) at least two charge-storage layers formed around a periphery of the columnar semiconductor portion and divided in a direction vertical to the semiconductor substrate, and (iii) a control gate that covers at least a portion of charge-storage layers, wherein the memory cell is capable of holding two-bit or more data.

Abstract: A memory cell in a semiconductor memory device comprises a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element and the variable resistor element are placed one over the other along a direction in which the first electrode, the variable resistor body, and the second electrode of the variable resistor element are layered, and one of the first electrode and the second electrode of the variable resistor element is connected to one electrode of the transistor element.

Abstract: A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the

Abstract: The present invention provides a semiconductor memory device comprising: a first conductivity type semiconductor substrate; and a plurality of memory cells constituted of an island-like semiconductor layer which is formed on the semiconductor substrate, and a charge storage layer and a control gate which are formed entirely or partially around a sidewall of the island-like semiconductor layer, wherein the plurality of memory cells are disposed in series, the island-like semiconductor layer which constitutes the memory cells has cross-sectional areas varying in stages in a horizontal direction of the semiconductor substrate, and an insulating film capable of passing charges is provided at least in a part of a plane of the island-like semiconductor layer horizontal to the semiconductor substrate.

Abstract: An ion implantation method for implanting ions into a side wall of a protruded semiconductor layer from a semiconductor substrate, the method includes applying an electric field to accelerate the ions in one direction and applying a magnetic field parallel to a plane extending at a predetermined angle with respect to the one direction, thereby controlling a direction of the ion implantation to the side wall.