Patents by Inventor Shinji Kanagu

Shinji Kanagu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030073372
    Abstract: In accordance with the present invention, there is provided a method of manufacturing a plasma display panel of the type which includes a discharge space defined between a pair of substrates and sealed by a sealant, the method comprising a first step of forming the sealant on at least one of the substrates and stacking one substrate on the other through the intermediation of the sealant, a second step of reducing the pressure in the space existing between the pair of substrates due to the presence of the sealant and melting the sealant by heating, a third step of curing the sealant to thereby firmly attach the pair of substrates to each other and define a predetermined discharge space, a fourth step of removing impurities in the discharge space, and a fifth step of filling the discharge space with discharge gas.
    Type: Application
    Filed: June 24, 1999
    Publication date: April 17, 2003
    Inventors: FUMIAKI NAKATAKE, MINORU FUKUI, YOSHITAKA UKAI, SHINJI KANAGU, KAZUHIDE IWASAKI, AKIHIRO FUJIMOTO
  • Patent number: 6538380
    Abstract: A plasma display panel has front and back substrates, each in a warped state in which a central portion of the substrate projects forwardly relatively to a peripheral portion thereof, presenting a convex front surface, a stress produced in the front and rear substrates pressing the front and rear substrates together with an elastic deformation. A height difference ratio of a central portion, measured from a central part of a short side, of each substrate, divided by a longitudinal width of the substrate is preferably less than 0.1% for each of the substrates.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: March 25, 2003
    Assignee: Fujitsu Limited
    Inventors: Shinji Kanagu, Masashi Amatsu
  • Publication number: 20020063664
    Abstract: A full color three electrode surface discharge type plasma display device that has fine image elements and is large and has a bright display. The three primary color luminescent areas are arranged in the extending direction of the display electrode pairs in a successive manner and an image element is composed by the three unit luminescent areas defined by these three luminescent areas and address electrodes intersecting these three luminescent areas. Further, phosphors are coated not only on a substrate but also on the side walls of the barriers and on address electrodes. The manufacturing processes and operation methods of the above constructions are also disclosed.
    Type: Application
    Filed: November 27, 2001
    Publication date: May 30, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Tsutae Shinoda, Noriyuki Awaji, Shinji Kanagu, Tatsutoshi Kanae, Masayuki Wakitani, Toshiyuki Nanto, Mamaru Miyahara
  • Publication number: 20020047519
    Abstract: A plasma display panel is provided that has a good productivity of partition formation and air exhaustion process and realizes a bright and stable display. A discharge gas is filled in a gap between two substrates. A mesh-patterned partition is arranged on the inner surface of one of the substrates for dividing the gap into plural squares corresponding to a cell arrangement. The partition has low portions for forming a mesh-like air path that travels all gas-filled space enclosed by the partition in a plan view.
    Type: Application
    Filed: February 8, 2001
    Publication date: April 25, 2002
    Inventors: Yasuhiko Kunii, Masayuki Shibata, Yoshimi Kawanami, Kenichi Yamamoto, Atsushi Yokoyama, Yusuke Yajima, Shinji Kanagu, Yasuhiro Wakabayashi, Akihiro Fujimoto, Toshiyuki Nanto
  • Patent number: 6195070
    Abstract: A full color three electrode surface discharge type plasma display device that has fine image elements and is large and has a bright display. The three primary color luminescent areas are arranged in the extending direction of the display electrode pairs in a successive manner and an image element is composed by the three unit luminescent areas defined by these three luminescent areas and address electrodes intersecting these three luminescent areas. Further, phosphors are coated not only on a substrate but also on the side walls of the barriers and on address electrodes. The manufacturing processes and operation methods of the above constructions are also disclosed.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: February 27, 2001
    Assignee: Fujitsu Limited
    Inventors: Tsutae Shinoda, Noriyuki Awaji, Shinji Kanagu, Tatsutoshi Kanae, Masayuki Wakitani, Toshiyuki Nanto, Mamaru Miyahara
  • Patent number: 6159066
    Abstract: It is an object of the present invention to prevent deterioration of a transparent electrically-conductive film which forms display electrodes, so as to enhance the reliability of display electrodes. In an AC type plasma display panel including a plurality of display electrodes X & Y formed of a transparent electrically-conductive film or a multiple layer of a transparent electrically-conductive film plus a metal film a width of which is narrower therethan, and a dielectric layer to cover the display electrodes from the discharge space, the dielectric layer is formed by the use of a ZnO-containing glass material containing substantially none of lead. Moreover, the display electrodes are protected by coating the dielectric layer so far as the ends of display electrodes; and the coating is removed afterwards by etching, etc.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: December 12, 2000
    Assignee: Fujitsu Limited
    Inventors: Masashi Amatsu, Shinji Kanagu, Masaaki Sasaka, Noriyuki Awaji, Kazumi Ebihara
  • Patent number: 6097357
    Abstract: A matrix display panel of first and second substrates having respective main surfaces in parallel and opposed relationship has parallel address electrodes and respective continuous phosphor stripes arranged within corresponding elongated cavities on the main surface of the first substrate, extending in a first direction. Display electrodes on the main surface of the second substrate extend in a second, transverse direction and cross the address electrodes and respective phosphor stripes, each display electrode defining a display line of pixels.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: August 1, 2000
    Assignee: Fujitsu Limited
    Inventors: Tsutae Shinoda, Noriyuki Awaji, Shinji Kanagu, Tatsutoshi Kanae, Masayuki Wakitani, Toshiyuki Nanto, Mamaru Miyahara
  • Patent number: 5977708
    Abstract: An electrode substrate of an AC type plasma display panel has a major surface with electrically connected display electrodes formed thereon and defining a display portion of the substrate. An insulating layer, of a ZnO-containing glass material containing substantially no lead, is formed on and covers the display portion of the major surface. The display electrodes may be a film of a transparent electrically-conducted material or a multi-layer film combination of a transparent electrically-conducted film of a first width and a metal film of a second, narrower width.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: November 2, 1999
    Assignee: Fujitsu Limited
    Inventors: Masashi Amatsu, Shinji Kanagu
  • Patent number: 5846110
    Abstract: Front substrate and back substrate of a PDP are respectively in a warped state such that a central portion of each substrate projects more frontwards than peripheral portions of the respective substrate, so that the front surface is convex. A stress remains in the substrates such that the two substrates are pressed to each other with an elastic deformation.In preparing the two substrates, the front panel and back panel are respectively warped towards each other so that the facing inner surfaces are convex in being sealed with each other. A height difference ratio of the central portion from a central part of a short side of the back substrate is preferably less than 0.16%. A height difference ratio of the central portion from a central part of a short side of the front substrate is preferably less than 0.06%. Difference of the height difference ratios of the back substrate and the front substrate is preferably 0 to 0.1 point.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: December 8, 1998
    Assignee: Fujitsu Limited
    Inventors: Shinji Kanagu, Masashi Amatsu
  • Patent number: 5674553
    Abstract: A full color three electrode surface discharge type plasma display device that has fine image elements and is large and has a bright display. The three primary color luminescent areas are arranged in the extending direction of the display electrode pairs in a successive manner and an image element is composed by the three unit luminescent areas defined by these three luminescent areas and address electrodes intersecting these three luminescent areas. Further, phosphors are coated not only on a substrate but also on the side walls of the barriers and on address electrodes. The manufacturing processes and operation methods of the above constructions are also disclosed.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: October 7, 1997
    Assignee: Fujitsu Limited
    Inventors: Tsutae Shinoda, Noriyuki Awaji, Shinji Kanagu, Tatsutoshi Kanae, Masayuki Wakitani, Toshiyuki Nanto, Mamaru Miyahara
  • Patent number: 5661500
    Abstract: A full color three electrode surface discharge type plasma display device that has fine image elements and is large and has a bright display. The three primary color luminescent areas are arranged in the extending direction of the display electrode pairs in a successive manner and an image element is composed by the three unit luminescent areas defined by these three luminescent areas and address electrodes intersecting these three luminescent areas. Further, phosphors are coated not only on a substrate but also on the side walls of the barriers and on address electrodes. The manufacturing processes and operation methods of the above constructions are also disclosed.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 26, 1997
    Assignee: Fujitsu Limited
    Inventors: Tsutae Shinoda, Noriyuki Awaji, Shinji Kanagu, Tatsutoshi Kanae, Masayuki Wakitani, Toshiyuki Nanto, Mamaru Miyahara