Patents by Inventor Shinji Miyamoto

Shinji Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7381855
    Abstract: An industrially advantageous process for producing adamantane by which high-purity adamantane reduced in coloration is efficiently produced while minimizing the loss. The process, which is for producing adamantane by isomerizing trimethylenenorbornane, includes (A) a reaction step of isomerizing the starting material, (B) a concentration step of concentrating the adamantane contained in the resultant liquid reaction mixture, (C) a crystallization step of precipitating the concentrated adamantane, (D) a solid-liquid separation step of separating the adamantane crystals from the slurry resulting from the crystallization, (E) a washing step of washing the isolated adamantane crystals, and (F) a drying step of drying the adamantane crystals washed, characterized in that the mass ratio of the endo-trimethylenenorbornane to the adamantane each contained in the materials to be subjected to the crystallization step (C) (endo-trimethylenenorbornane/adamantane) is 0.25 or lower.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: June 3, 2008
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Jun Mase, Shinji Miyamoto, Akio Kojima, Masao Saito, Toshiaki Kusaba
  • Publication number: 20070280077
    Abstract: In order to decrease alternate processing when a verification error is detected for an optical storage medium, a position BS and a length BL of a defect are stored when a verification error is detected, and based on this stored information, rewriting is performed with increasing the write power for the defective section. Thereby even if an LD driver with simple configuration and low price, which is used for APC control for a digital feedback loop by firmware, is used, the emission power can be increased only for the defective section, and the reproducing waveform of the defective section can be increased, and the use of alternate sectors can be decreased when writing is retried.
    Type: Application
    Filed: August 7, 2007
    Publication date: December 6, 2007
    Applicant: Fujitsu Limited
    Inventor: Shinji Miyamoto
  • Publication number: 20070173678
    Abstract: An industrially advantageous process for producing adamantane by which high-purity adamantane reduced in coloration is efficiently produced while minimizing the loss. The process, which is for producing adamantane by isomerizing trimethylenenorbornane, includes (A) a reaction step of isomerizing the starting material, (B) a concentration step of concentrating the adamantane contained in the resultant liquid reaction mixture, (C) a crystallization step of precipitating the concentrated adamantane, (D) a solid-liquid separation step of separating the adamantane crystals from the slurry resulting from the crystallization, (E) a washing step of washing the isolated adamantane crystals, and (F) a drying step of drying the adamantane crystals washed, characterized in that the mass ratio of the endo-trimethylenenorbornane to the adamantane each contained in the materials to be subjected to the crystallization step (C) (endo-trimethylenenorbornane/adamantane) is 0.25 or lower.
    Type: Application
    Filed: February 28, 2005
    Publication date: July 26, 2007
    Applicant: Idemitsu Kosan Co., Ltd
    Inventors: Jun Mase, Shinji Miyamoto, Akio Kojima, Masao Saito, Toshiaki Kusaba
  • Publication number: 20070156002
    Abstract: The present invention provides a process of an industrially advantageous production of high-purity adamantane at a low cost and with a high efficiency by isomerizing trimethylenenorbornane contained in a raffinate obtained from a platfinate.
    Type: Application
    Filed: December 16, 2004
    Publication date: July 5, 2007
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Akio Kojima, Masao Saito, Shinji Miyamoto, Jun Mase, Toyozo Fujioka
  • Patent number: 7119802
    Abstract: A compact-size driving voltage controller is provided which can be driven with low power. The compact-size driving voltage controller which can be driven with low power includes a High output operational amplifier and a Low output operational amplifier for supplying driving voltages VcomH, VcomL to a load such as a liquid crystal display panel, an output switch for alternating between the outputs of the operational amplifiers, a Low voltage setting operational amplifier for generating a set voltage to be supplied to the non-inverted input terminal of the Low output operational amplifier, a set voltage generator including a current mirror circuit and a clamping circuit, a bias current controller for controlling the bias current flowing in each operational amplifier with a predetermined timing, and a timing controller for controlling the changeover timing of the output switch.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: October 10, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tooru Suyama, Tsutomu Sakakibara, Tomokazu Kojima, Tetsuro Ohmori, Yoshito Date, Yasuyuki Doi, Masahiro Akabori, Kenji Miyake, Miki Fujino, Takahito Kushima, Tsukasa Kawahara, Kazuhiko Nagaoka, Shinji Miyamoto, Yoshiyuki Konishi
  • Publication number: 20060111596
    Abstract: According to the present invention, there is provided a process for producing adamantanes by isomerizing a tricyclic saturated hydrocarbon compound having 10 or more carbon atoms, comprising (A) a reaction step for isomerizing a raw material, (B) a concentration step for concentrating the adamantanes in a reaction product liquid, (C) a crystallization step for crystallizing the concentrated adamantanes, (D) a solid-liquid separation step for separating the crystallized adamantanes from slurry having precipitated crystals, (E) a washing step for washing the crystal of adamantanes obtained by the solid-liquid separation step, and (F) a drying step for drying the washed crystals of adamantanes. According to the present invention, there is provided a process for producing adamantanes by using a solid catalyst, wherein the obtained adamantanes are purified by a crystallization operation.
    Type: Application
    Filed: July 25, 2003
    Publication date: May 25, 2006
    Applicant: Idemitsu Kosan Co., Ltd.
    Inventors: Jun Mase, Shinji Miyamoto, Akio Kojima, Masao Saito
  • Publication number: 20040062164
    Abstract: An apparatus automatically controls the laser power of the light source by the feedback output of the APC detector and prevents the increase of laser power due to an abnormality of the APC detector. The automatic power control unit controls the drive amount of the light source by the detection output of the APC detector, which monitors the emission power of the light source, measures the relationship between the APC drive instruction amount and the detection output of the APC detector, and compares this inclination with the inclination at normal time. Also the automatic power control unit compares the error values before and after APC, and detects the change of the quantity of returned light during a predetermined period. As a result, data destruction due to separation, deviation, contamination or deterioration of the APC detector can be prevented effectively.
    Type: Application
    Filed: September 17, 2003
    Publication date: April 1, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Shinji Miyamoto, Yuji Karakawa, Toru Ikeda, Takashi Masaki, Masatsugu Nishida
  • Publication number: 20030151581
    Abstract: The present invention provides a compact-size driving voltage controller which can be driven with low power. The compact-size driving voltage controller which can be driven with low power includes a High output operational amplifier and a Low output operational amplifier for supplying driving voltages VcomH, VcomL to a load such as a liquid crystal display panel, an output switch for alternating between the outputs of the operational amplifiers, a Low voltage setting operational amplifier for generating a set voltage to be supplied to the non-inverted input terminal of the Low output operational amplifier, a set voltage generator including a current mirror circuit and a clamping circuit, a bias current controller for controlling the bias current flowing in each operational amplifier with a predetermined timing, and a timing controller for controlling the changeover timing of the output switch.
    Type: Application
    Filed: January 24, 2003
    Publication date: August 14, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tooru Suyama, Tsutomu Sakakibara, Tomokazu Kojima, Tetsuro Ohmori, Yoshito Date, Yasuyuki Doi, Masahiro Akabori, Kenji Miyake, Miki Fujino, Takahito Kushima, Tsukasa Kawahara, Kazuhiko Nagaoka, Shinji Miyamoto, Yoshiyuki Konishi
  • Patent number: 6320803
    Abstract: There is provided method and apparatus for improving and making more effective the testing of very large scale integrated (VLSI) devices such as a synchronous random access memory (SDRAM), along with improving their performance and their yield in production. The method includes the steps of providing a VLSI device with switching circuitry which permits respective arrays or banks of the device to be tested alone or simultaneously with separate sequences of test mode signals to identify defects, interactions and unwanted limitations in the overall performance of the device; using the information thus obtained to modify the test mode signals and where indicated the design of the device; iterating the previous steps to optimize a test methodology for the device; and using the optimized test methodology during burn-in of production devices. Logic circuitry is added to a VLSI device to facilitate the improved testing capability.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: November 20, 2001
    Assignees: Infineon Technologies AC, Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Martin Gall, Wayne Ellis, Shinji Miyamoto, Masahiro Yoshihara
  • Patent number: 6260128
    Abstract: A clock signal is supplied to an input buffer circuit. A delay circuit has a delay time equal to a difference between the cycle time for latency (CL) of 3 and the cycle time for latency of 2. When CL=2, a transfer gate outputs a clock signal delayed by the delay circuit, as a clock signal CLK2. The clock signal CLK2 initiates the operation in the second stage at the latency of 3. The operation at the latency of 2 can, therefore, be performed in a cycle time having a sufficient margin, without increasing the speed of the operation in the second stage at the latency of 3.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: July 10, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Ohshima, Shinji Miyamoto
  • Patent number: 5287306
    Abstract: A semiconductor memory device includes a first power source having a non-ground potential V.sub.cc1 terminal and a ground potential V.sub.ss1 terminal. The internal circuit is supplied with power from the first power source. The first power source is dedicated to the internal circuit. The internal circuit selects a memory cell of a memory cell array in accordance with an inputted address. The internal circuit has a first output terminal and a second output terminal the first output terminal outputs one of a pair of potential V.sub.cc1 and V.sub.ss1 and the second output terminal outputs the other of the pair in accordance with the data in the selected memory cell. A second power source has a non-ground potential V.sub.cc2 terminal and a ground potential V.sub.ss2 terminal. The output circuit is supplied with power from the second power source which is dedicated to the output circuit. The output circuit has first and second transistors serially connected between the V.sub.cc2 terminal and V.sub.ss2.
    Type: Grant
    Filed: June 20, 1991
    Date of Patent: February 15, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Miyamoto, Shigeo Ohshima
  • Patent number: 5138581
    Abstract: A multiport memory has a RAM port including a memory cell array having a plurality of memory cells arranged in a matrix form, sense amplifier circuit for sensing potential of a bit line after the storage potential has been transferred from the memory cells, restore circuit connected to the bit line for pulling up the potential of the bit line at the predetermined timing after sense operation has been started and a barrier circuit connected between the bit line and the sense amplifier circuit; and a SAM port including a data register, transfer gate and functional means for transferring serial data in the column direction. In this memory, the RAM port is connected to the SAM port by the transfer gate with the bit line directly connected to the data register, and the potentials at the bit line are amplified by the sense amplifier circuit and are directly transferred to the data register.
    Type: Grant
    Filed: September 5, 1990
    Date of Patent: August 11, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Miyamoto, Shigeo Ohshima
  • Patent number: 4785382
    Abstract: A retractable lamp device for vehicles includes a vehicles includes a vehicle body having a space for accommodating a lamp, a cover member rotatably mounted on the body to open or close the space, a motor for rotating the cover member. The retractable lamp further includes a movable member connected to the motor and an adjusting member for adjusting the surface level of the vehicle body and the cover member from outside of the vehicle.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: November 15, 1988
    Assignees: Aisin Seiki Kabushiki Kaisha, Kanto Jidosha Kogyo Kabushiki Kaisha
    Inventors: Kenichi Fukura, Hiroki Kondo, Yoshinori Kuroyanagi, Morito Kawaguchi, Shinji Miyamoto, Eiji Hiramatsu, Akira Nishimura, Etsuo Suzuki, Kazuo Ikuta