Abstract: In a nonvolatile semiconductor memory device, a high voltage is selectively exerted between a word line to which the control gates of nonvolatile semiconductor memory elements are coupled and a source line to which the sources of the nonvolatile semiconductor memory elements are coupled, whereby charges stored in the floating gates are extracted through the source line. In addition, the nonvolatile semiconductor memory elements to be erased are provided with a source potential having ramp-rate characteristics such that the sources are gradually raised from a low voltage to the high voltage. Thus, the erasure of a predetermined part of the memory array of the memory device becomes possible in accordance with the division of the source lines or that of the word lines, and an excessive intense electric field can be prevented from acting between the floating gates and the sources because a ramp rate is used for the erasing high voltage.

Abstract: A semiconductor integrated circuit device enabled to perform both a normal writing operation using a voltage elevated with the internal supply voltage taken as the reference voltage and a writing operation with the use of another voltage elevated with an external voltage applied to an external terminal taken as the reference voltage, whereby margin measurement, high-voltage test, and accelerated test are enabled to be performed even after packaging. Further, by providing the apparatus with a mode selector having a plurality of latch circuits operating at different timing connected to an input terminal so that modes are switched by changing combination of the signals latched in such latch circuits, the number of operating modes can be increased without increasing the number of pins.

Abstract: A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into said semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an eronneous operation from developing when the power source is closed, provision is made of a power souce closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is prevented from being applied to the memory element from the time from when the power source circuit is closed up to the time when the read operation mode is designated by an external control signal.

Abstract: Using a comparatively low supply voltage of, e.g., +5V and a minus gate voltage, the voltage difference between the gate of an MNOS transistor and a P-type well region in which a MNOS transistor is formed is relatively changed to execute the writing and erasing of the MNOS transistor. Thus, the potential of an N-type semiconductor substrate can be fixed to a comparatively low potential, e.g., about +5V, so that a P-channel MOSFET formed on the semiconductor substrate operates with an ordinary signal level. Consequently, an EEPROM having peripheral circuits constructed of CMOS circuits can be provided. Accordingly, reduction in the power consumption of the EEPROM can be attained.

Abstract: A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into the semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an erroneous operation from developing when the power source is closed, provision is made of a power source closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is being applied to the memory element from the time from when the power source circuit is closed up to the times when the read operation mode is designated by an external control signal.

Abstract: A nonvolatile memory which has both the merits of a floating gate type EEPROM and an MNOS type EEPROM and which can be written into and erased with low voltages is disclosed. Each memory element in the nonvolatile memory has a floating gate, a control gate, a gate insulator film between a semiconductor body and the floating gate, and an inter-layer insulator film between the control gate and the floating gate. The gate insulator film is made up of a very thin SiO.sub.2 film and a thin Si.sub.3 N.sub.4 film formed thereon. The charge centroid of charges injected for storing data lies within the floating gate, not within the Si.sub.3 N.sub.4 film.