Patents by Inventor Shinji Nakahara
Shinji Nakahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9340900Abstract: A method of producing an epitaxial wafer, comprising: performing epitaxial growth of silicon on a main surface of a wafer made of a silicon single crystal; performing surface flattening pretreatment of a main surface of the wafer using a treatment liquid of a predetermined composition at a temperature of 100° C. or less, thereby forming an oxide film of a predetermined thickness while removing particles adhered on the main surface of the wafer; and performing a surface polishing step where the main surface of the wafer is mirror polished.Type: GrantFiled: September 5, 2007Date of Patent: May 17, 2016Assignee: Sumco CorporationInventors: Shinji Nakahara, Masato Sakai, Takayuki Dohi
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Patent number: 8815710Abstract: Disclosed is a wafer having a good haze level in spite of the fact that the inclination angle of {110} plane in the wafer is small. Also disclosed is a method for producing a silicon epitaxial wafer, which comprises the steps of: growing an epitaxial layer on a silicon single crystal substrate having a main surface of {110} plane of which an off-angle is less than 1 degree; and polishing the surface of the epitaxial layer until the surface of the epitaxial layer has a haze level of 0.18 ppm or less (as measured by SP2 at a DWO mode).Type: GrantFiled: April 17, 2009Date of Patent: August 26, 2014Assignee: Sumco CorporationInventors: Masayuki Ishibashi, Shinji Nakahara, Tetsuro Iwashita
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Patent number: 8580148Abstract: It is an object of the present invention to provide an alkaline earth metal aluminate phosphor having good heat resistance and durability against vacuum ultraviolet rays and ultraviolet rays, among others, and a method of producing the same. An alkaline earth metal aluminate phosphor containing bivalent europium as an activator, which contains at least one element (e) selected from the group consisting of indium, tungsten, niobium, bismuth, molybdenum, tantalum, thallium and lead.Type: GrantFiled: March 12, 2004Date of Patent: November 12, 2013Assignee: Sakai Chemical Industry Co., Ltd.Inventors: Seiko Hirayama, Keita Kobayashi, Junya Ishii, Mizuho Wada, Shinji Nakahara
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Patent number: 8518848Abstract: A titanium oxide photocatalyst that is capable of improving a decomposition rate, and a method for producing the same are provided. The titanium oxide photocatalyst of the present invention is a titanium oxide photocatalyst containing at least an anatase-type titanium oxide and fluorine, wherein a content of the fluorine is 2.5 wt % to 3.5 wt %, and 90 wt % or more of the fluorine is chemically bonded to the anatase-type titanium oxide.Type: GrantFiled: February 29, 2012Date of Patent: August 27, 2013Assignees: Panasonic Corporation, Sakai Chemical Industry Co., Ltd.Inventors: Noboru Taniguchi, Shuzo Tokumitsu, Tomohiro Kuroha, Kenichi Tokuhiro, Akio Nakashima, Keita Kobayashi, Shinji Nakahara
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Publication number: 20120157300Abstract: A titanium oxide photocatalyst that is capable of improving a decomposition rate, and a method for producing the same are provided. The titanium oxide photocatalyst of the present invention is a titanium oxide photocatalyst containing at least an anatase-type titanium oxide and fluorine, wherein a content of the fluorine is 2.5 wt % to 3.5 wt %, and 90 wt % or more of the fluorine is chemically bonded to the anatase-type titanium oxide.Type: ApplicationFiled: February 29, 2012Publication date: June 21, 2012Applicants: SAKAI CHEMICAL INDUSTRY CO., LTD., PANASONIC CORPORATIONInventors: Noboru TANIGUCHI, Shuzo TOKUMITSU, Tomohiro KUROHA, Kenichi TOKUHIRO, Akio NAKASHIMA, Keita KOBAYASHI, Shinji NAKAHARA
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Patent number: 8152919Abstract: An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a <100> orientation parallel to the {110} plane toward a <100> direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100} wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.Type: GrantFiled: June 20, 2011Date of Patent: April 10, 2012Assignee: Sumco CorporationInventors: Takayuki Dohi, Shinji Nakahara, Masaya Sakurai, Masato Sakai
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Patent number: 8148289Abstract: A titanium oxide photocatalyst that is capable of improving a decomposition rate, and a method for producing the same are provided. The titanium oxide photocatalyst of the present invention is a titanium oxide photocatalyst containing at least an anatase-type titanium oxide and fluorine, wherein a content of the fluorine is 2.5 wt % to 3.5 wt %, and 90 wt % or more of the fluorine is chemically bonded to the anatase-type titanium oxide.Type: GrantFiled: April 18, 2008Date of Patent: April 3, 2012Assignees: Panasonic Corporation, Sakai Chemical Industry Co., Ltd.Inventors: Noboru Taniguchi, Shuzo Tokumitsu, Tomohiro Kuroha, Kenichi Tokuhiro, Akio Nakashima, Keita Kobayashi, Shinji Nakahara
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Publication number: 20110239931Abstract: An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a <100> orientation parallel to the {110} plane toward a <100> direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100} wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.Type: ApplicationFiled: June 20, 2011Publication date: October 6, 2011Applicant: SUMCO CORPORATIONInventors: Takayuki Dohi, Shinji Nakahara, Masaya Sakurai, Masato Sakai
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Patent number: 7989073Abstract: An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a <100> orientation parallel to the {110} plane toward a <110 > direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100 } wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.Type: GrantFiled: September 5, 2007Date of Patent: August 2, 2011Assignee: Sumco CorporationInventors: Takayuki Dohi, Shinji Nakahara, Masaya Sakurai, Masato Sakai
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Publication number: 20110031592Abstract: Disclosed is a wafer having a good haze level in spite of the fact that the inclination angle of {110} plane in the wafer is small. Also disclosed is a method for producing a silicon epitaxial wafer, which comprises the steps of: growing an epitaxial layer on a silicon single crystal substrate having a main surface of {110} plane of which an off-angle is less than 1 degree; and polishing the surface of the epitaxial layer until the surface of the epitaxial layer has a haze level of 0.18 ppm or less (as measured by SP2 at a DWO mode).Type: ApplicationFiled: April 17, 2009Publication date: February 10, 2011Applicant: SUMCO CORPORATIONInventors: Masayuki Ishibashi, Shinji Nakahara, Tetsuro Iwashita
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Publication number: 20100111817Abstract: A titanium oxide photocatalyst that is capable of improving a decomposition rate, and a method for producing the same are provided. The titanium oxide photocatalyst of the present invention is a titanium oxide photocatalyst containing at least an anatase-type titanium oxide and fluorine, wherein a content of the fluorine is 2.5 wt % to 3.5 wt %, and 90 wt % or more of the fluorine is chemically bonded to the anatase-type titanium oxide.Type: ApplicationFiled: April 18, 2008Publication date: May 6, 2010Applicants: PANASONIC CORPORATION, SAKAI CHEMICAL INDUSTRY CO., LTD.Inventors: Noboru Taniguchi, Shuzo Tokumitsu, Tomohiro Kuroha, Kenichi Tokuhiro, Akio Nakashima, Keita Kobayashi, Shinji Nakahara
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Publication number: 20100047590Abstract: The object of the present invention is to provide an ultrafine zinc oxide having a sufficient visible light transmittance in addition to an infrared ray shielding ability and conductivity, and also to provide a production method thereof. The ultrafine zinc oxide contains an element having a valence number of 3 or more, bears a metal compound on the surface, and has an average primary particle diameter of 0.1 ?m or smaller.Type: ApplicationFiled: September 26, 2007Publication date: February 25, 2010Inventors: Emi Ueda, Keita Kobayashi, Shinji Nakahara
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Publication number: 20080057323Abstract: An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a <100> orientation parallel to the {110} plane toward a <110> direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100} wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.Type: ApplicationFiled: September 5, 2007Publication date: March 6, 2008Applicant: SUMCO CORPORATIONInventors: Takayuki Dohi, Shinji Nakahara, Masaya Sakurai, Masato Sakai
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Publication number: 20080057324Abstract: A method of producing an epitaxial wafer, comprising: performing epitaxial growth of silicon on a main surface of a wafer made of a silicon single crystal; performing surface flattening pretreatment of a main surface of the wafer using a treatment liquid of a predetermined composition at a temperature of 100° C. or less, thereby forming an oxide film of a predetermined thickness while removing particles adhered on the main surface of the wafer; and performing a surface polishing step where the main surface of the wafer is mirror polished.Type: ApplicationFiled: September 5, 2007Publication date: March 6, 2008Applicant: SUMCO CORPORATIONInventors: Shinji Nakahara, Masato Sakai, Takayuki Dohi
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Patent number: 6863735Abstract: An epitaxial growth furnace is provided for effecting the formation of an epitaxial layer on the surface of a semiconductor wafer by CVD in a reaction chamber of the furnace. The furnace comprises a wafer holder having an opening for exposing a surface area of the wafer which is subject to epitaxial growth, an opening flange adapted for engagement with a chamfered tapered face of a whole peripheral edge of the wafer on the side of said surface area thereof, and a plurality of jaws for detachably engaging with an outer periphery of the wafer on a back surface side of said surface area.Type: GrantFiled: July 26, 1999Date of Patent: March 8, 2005Assignee: Super Silicon Crystal Research Institute Corp.Inventors: Shinji Nakahara, Masato Imai, Masanori Mayusumi, Kazutoshi Inoue, Shintoshi Gima
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Publication number: 20030159472Abstract: A laser beam emitted from a laser element is received by a laser receiver. The soot deposition process is carried out by controlling a growing shoot deposition surface at a constant specified position based upon information carried by the received laser beam. The laser receiver is provided with a filter for absorbing heat rays generated by a burner flame and a heat shielding plate made of material having a high heat resistance to prevent the temperature of the receiver from rising. The receiver is also cooled with a stream of cooling gas. The above-described arrangement can prevent the occurrence of malfunction of the sensor portion due to its temperature rise and assures the reliable position control of the soot deposition, achieving a high accuracy of the soot perform produced.Type: ApplicationFiled: February 6, 2003Publication date: August 28, 2003Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shinji Nakahara, Tatsuo Saito, Kazuki Kunitake
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Patent number: 6578589Abstract: Disclosed is a compact apparatus for manufacturing semiconductor wafers, which is aimed at complete removing of moisture from the wafers after final cleaning while reducing the manufacturing time. The apparatus includes a cleaning chamber (1) for final cleaning, a storage chamber (3) for storing wafers, a transfer chamber (2) communicating with the both cleaning and storage chambers (1, 3), and formed in its upper wall with a heat-conducting window (7), a robot hand (5) and a robot arm (4) for transporting the wafer (W) from the cleaning chamber (1) to the storage chamber (3) within the transfer chamber, infrared lamps (6) arranged to face the window (7) outside the transfer chamber (2) so as to heat the wafer (W) in the course of transportation within the transfer chamber, gas supply ports (8) for producing a laminar flow of inert gas from the storage chamber (3) to the cleaning chamber (1) to expose wafers (W) with the gas, and exhaust ports (9) for exhausting the moisture removed from wafers.Type: GrantFiled: September 24, 2001Date of Patent: June 17, 2003Assignee: Super Silicon Crystal Research Institute Corp.Inventors: Masanori Mayusumi, Masato Imai, Kazutoshi Inoue, Shinji Nakahara, Shintoshi Gima
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Patent number: 6323140Abstract: Disclosed is a method for manufacturing a semiconductor wafer having an epitxial layer on a surface thereof, by the steps of forming a pritective oxide film on a surface of a semiconductor wafer prior to loading of the wafer into an eptaxial growth furnace, removing the protective oxide film formed on the surface of the wafer by heating after the wafer is loaded in the furnace, and performing epitaxial growth of the epitaxial layer on the surface from which the protective oxide film is removed in the furnace. The protective oxide film is removed by heating the wafer in the furnace in an ambience of hydrogen gas at a pressure ranging from 0.0133×105 Pa to 1.013×105 Pa and at a temperature ranging from 800° C. to 1,000 ° C., or by heating the wafer in the furnace at a pressure of 5×106 Pa or under and at a temperature ranging from 800° C. to 1,000° C.Type: GrantFiled: February 26, 2001Date of Patent: November 27, 2001Assignee: Silicon Crystal Research Institute Corp.Inventors: Masanori Mayusumi, Masato Imai, Kazutoshi Inoue, Shinji Nakahara
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Patent number: 6262393Abstract: An epitaxial growth furnace comprising first and second partition walls arranged within a reaction chamber, a first separate space surrounded by the partition walls and the inner wall surface of the reaction chamber, a second separate space partitioned by the partition walls so as to be isolated from the inner wall surface of the reaction chamber, a holding mechanism adapted to hold a pair of semiconductor wafers respectively on the first and second partition walls so that the principal surfaces of the pair of wafers face each other with spacing therebetween and are also exposed to the second separate space, and a pair of heaters for respectively irradiating radiant heat to the back surfaces of the two wafers.Type: GrantFiled: October 16, 2000Date of Patent: July 17, 2001Assignee: Super Silicon Crystal Research Institute Corp.Inventors: Masato Imai, Masanori Mayusumi, Shinji Nakahara, Kazutoshi Inoue
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Patent number: 6245152Abstract: A method and apparatus for forming an epitaxial layer on a semiconductor wafer supported on a suscepter in an epitaxial growth furnace. Ther wafer to be processed is placed on the suscepter outside the furnace. The suscepter carrying the wafer is transferred into the furnace from the outside thereof and mounted in a loading position within the furnace. An epitaxial growth process is then performed on the wafer on the suscepter mounted in the loading position. After the completion of the growth process, the suscepter carrying the wafer thereon is removed from the furnace loading position and transferred to the outside of the furnace.Type: GrantFiled: June 30, 1997Date of Patent: June 12, 2001Assignee: Super Silicon Crystal Research Institute Corp.Inventors: Masato Imai, Masanori Mayusumi, Shinji Nakahara, Kazutoshi Inoue