Patents by Inventor Shinji Nakatsuka
Shinji Nakatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11836403Abstract: A schedule adjustment apparatus includes a storage portion, an acquisition portion, and an adjustment portion. The storage portion stores a schedule for giving an instruction to perform maintenance of the image forming apparatus. The acquisition portion acquires, from the image forming apparatus, state information indicating a state of an image formed on a sheet by the image forming apparatus. The adjustment portion adjusts the schedule based on the state information.Type: GrantFiled: August 24, 2022Date of Patent: December 5, 2023Assignee: KYOCERA Document Solutions Inc.Inventor: Shinji Nakatsuka
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Publication number: 20230064640Abstract: A schedule adjustment apparatus includes a storage portion, an acquisition portion, and an adjustment portion. The storage portion stores a schedule for giving an instruction to perform maintenance of the image forming apparatus. The acquisition portion acquires, from the image forming apparatus, state information indicating a state of an image formed on a sheet by the image forming apparatus. The adjustment portion adjusts the schedule based on the state information.Type: ApplicationFiled: August 24, 2022Publication date: March 2, 2023Inventor: Shinji Nakatsuka
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Patent number: 11025241Abstract: A comparator circuit includes a differential input circuit, a load circuit, a first current source, a first bias voltage supplying circuit, a third connection circuit, and a fourth connection circuit. The differential input circuit includes a first transistor to which a first input signal is supplied and a second transistor to which a second input signal is supplied. The load circuit includes a third transistor connected to the first transistor through a first connection circuit and a fourth transistor connected to the second transistor through a second connection circuit, gates of the third and fourth transistors being connected to the first connection circuit through a third capacitor. The first bias voltage supplying circuit supplies a first bias voltage to the gates of the third and fourth transistors and the third capacitor.Type: GrantFiled: December 5, 2019Date of Patent: June 1, 2021Inventors: Shinji Nakatsuka, Koji Mishina, Noriyuki Fukushima
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Patent number: 10956098Abstract: An image forming system includes a plurality of processing apparatuses. An image forming apparatus includes an image forming section, storage, an acquiring section, a first specifying section, a receiver, a second specifying section, and a notifying section. The storage stores therein a position of each of the processing apparatuses. The acquiring section acquires state information from each of the processing apparatuses. The state information indicates whether a corresponding one of the processing apparatuses is in a normal function state or a malfunction state. The first specifying section specifies, from among the processing apparatuses, a malfunctioning processing apparatus for which the malfunction state is indicated by the state information. The second specifying section specifies a relative position of the malfunctioning processing apparatus with respect to a mobile terminal device.Type: GrantFiled: October 28, 2019Date of Patent: March 23, 2021Assignee: KYOCERA Document Solutions Inc.Inventors: Shinji Nakatsuka, Makoto Kowaka, Hironori Okamoto, Kentaro Kishida, Koichiro Tazuke, Masakazu Yamamoto
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Publication number: 20200204170Abstract: A comparator circuit includes a differential input circuit, a load circuit, a first current source, a first bias voltage supplying circuit, a third connection circuit, and a fourth connection circuit. The differential input circuit includes a first transistor to which a first input signal is supplied and a second transistor to which a second input signal is supplied. The load circuit includes a third transistor connected to the first transistor through a first connection circuit and a fourth transistor connected to the second transistor through a second connection circuit, gates of the third and fourth transistors being connected to the first connection circuit through a third capacitor. The first bias voltage supplying circuit supplies a first bias voltage to the gates of the third and fourth transistors and the third capacitor.Type: ApplicationFiled: December 5, 2019Publication date: June 25, 2020Inventors: SHINJI NAKATSUKA, KOJI MISHINA, NORIYUKI FUKUSHIMA
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Publication number: 20200133589Abstract: An image forming system includes a plurality of processing apparatuses. An image forming apparatus includes an image forming section, storage, an acquiring section, a first specifying section, a receiver, a second specifying section, and a notifying section. The storage stores therein a position of each of the processing apparatuses. The acquiring section acquires state information from each of the processing apparatuses. The state information indicates whether a corresponding one of the processing apparatuses is in a normal function state or a malfunction state. The first specifying section specifies, from among the processing apparatuses, a malfunctioning processing apparatus for which the malfunction state is indicated by the state information. The second specifying section specifies a relative position of the malfunctioning processing apparatus with respect to a mobile terminal device.Type: ApplicationFiled: October 28, 2019Publication date: April 30, 2020Applicant: KYOCERA Document Solutions Inc.Inventors: Shinji NAKATSUKA, Makoto KOWAKA, Hironori OKAMOTO, Kentaro KISHIDA, Koichiro TAZUKE, Masakazu YAMAMOTO
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Patent number: 10412256Abstract: An image reading device includes a first image reading portion, a cooling portion, a second image reading portion, and a notification processing portion. The first image reading portion reads an image of a document sheet at a first reading position. The cooling portion cools the document sheet at a cooling position downstream in a feeding direction of the document sheet with respect to the first reading position. The second image reading portion reads an image of the document sheet at a second reading position downstream in the feeding direction with respect to the cooling position. In a case where a difference image different from a first image read by the first image reading portion, the difference image being included in a second image read by the second image reading portion has been detected, the notification processing portion provides a notification that the difference image has been detected.Type: GrantFiled: November 28, 2017Date of Patent: September 10, 2019Assignee: KYOCERA Document Solutions Inc.Inventor: Shinji Nakatsuka
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Patent number: 10010262Abstract: An impedance measuring circuit has an amplification circuit connected to a target and to amplify a predetermined input signal with a gain corresponding to an impedance in the target and to output an output signal, a peak hold circuit to hold a peak value of the output signal and to output a hold value, and an impedance calculation circuit to calculate the impedance in the target based on the hold value.Type: GrantFiled: March 9, 2016Date of Patent: July 3, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Sinnyoung Kim, Shinji Nakatsuka, Daisuke Kurose
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Publication number: 20180152585Abstract: An image reading device includes a first image reading portion, a cooling portion, a second image reading portion, and a notification processing portion. The first image reading portion reads an image of a document sheet at a first reading position. The cooling portion cools the document sheet at a cooling position downstream in a feeding direction of the document sheet with respect to the first reading position. The second image reading portion reads an image of the document sheet at a second reading position downstream in the feeding direction with respect to the cooling position. In a case where a difference image different from a first image read by the first image reading portion, the difference image being included in a second image read by the second image reading portion has been detected, the notification processing portion provides a notification that the difference image has been detected.Type: ApplicationFiled: November 28, 2017Publication date: May 31, 2018Inventor: Shinji Nakatsuka
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Patent number: 9614555Abstract: According to an embodiment, a transmission circuit is configured to transmit a signal to a reception circuit through a transmitting AC coupling element. The transmitting AC coupling element is AC coupled to a receiving AC coupling element. The transmission circuit includes a drive signal generation circuit and a drive circuit. The drive signal generation circuit is configured to generate a drive signal in synchronization with a transmission signal to be transmitted. The drive circuit is configured to cause, in response to the drive signal, a drive current to flow between both ends of the transmitting AC coupling element in synchronization with a rising edge and a falling edge of the transmission signal during a driving period set in advance. The drive circuit is configured to apply an applied voltage to both of the ends of the transmitting AC coupling element after the driving period.Type: GrantFiled: September 4, 2015Date of Patent: April 4, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Nakatsuka, Shinsuke Fujii
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Publication number: 20170086702Abstract: An impedance measuring circuit has an amplification circuit connected to a target and to amplify a predetermined input signal with a gain corresponding to an impedance in the target and to output an output signal, a peak hold circuit to hold a peak value of the output signal and to output a hold value, and an impedance calculation circuit to calculate the impedance in the target based on the hold value.Type: ApplicationFiled: March 9, 2016Publication date: March 30, 2017Inventors: Sinnyoung Kim, Shinji Nakatsuka, Daisuke Kurose
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Patent number: 9484870Abstract: A device includes an operational-amplifier including an amplifier-part amplifying signals and transmitting amplified signals to a first and a second nodes, and an output-part connected to the first and second nodes and outputting signals from a first and a second outputs. The device includes a first and a second chopper switches and a first and second phase-compensation capacity elements. A first capacitance switch switches between a first connection-state and a second connection-state. In the first connection-state, the first phase-compensation-capacity element is connected between the first node and the first output and the second phase-compensation-capacity element is connected between the second node and the second-output. In the second connection state, the first phase-compensation-capacity element is connected between the second-node and the second output and the second phase-compensation-capacity element is connected between the first node and the first output.Type: GrantFiled: March 4, 2015Date of Patent: November 1, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Nakatsuka, Shigeo Imai, Yosuke Ogawa
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Publication number: 20160276989Abstract: A device includes an operational-amplifier including an amplifier-part amplifying signals and transmitting amplified signals to a first and a second nodes, and an output-part connected to the first and second nodes and outputting signals from a first and a second outputs. The device includes a first and a second chopper switches and a first and second phase-compensation capacity elements. A first capacitance switch switches between a first connection-state and a second connection-state. In the first connection-state, the first phase-compensation-capacity element is connected between the first node and the first output and the second phase-compensation-capacity element is connected between the second node and the second-output. In the second connection state, the first phase-compensation-capacity element is connected between the second-node and the second output and the second phase-compensation-capacity element is connected between the first node and the first output.Type: ApplicationFiled: March 4, 2015Publication date: September 22, 2016Inventors: Shinji Nakatsuka, Shigeo Imai, Yosuke Ogawa
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Publication number: 20160218755Abstract: According to an embodiment, a transmission circuit is configured to transmit a signal to a reception circuit through a transmitting AC coupling element. The transmitting AC coupling element is AC coupled to a receiving AC coupling element. The transmission circuit includes a drive signal generation circuit and a drive circuit. The drive signal generation circuit is configured to generate a drive signal in synchronization with a transmission signal to be transmitted. The drive circuit is configured to cause, in response to the drive signal, a drive current to flow between both ends of the transmitting AC coupling element in synchronization with a rising edge and a falling edge of the transmission signal during a driving period set in advance. The drive circuit is configured to apply an applied voltage to both of the ends of the transmitting AC coupling element after the driving period.Type: ApplicationFiled: September 4, 2015Publication date: July 28, 2016Inventors: Shinji Nakatsuka, Shinsuke Fujii
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Patent number: 9350306Abstract: According to one embodiment, an amplification circuit includes first and second differential amplification circuits, each having an output connected to an output terminal and a feedback resistor connected between the output and a negative input of the respective differential amplification circuit. The amplification circuit includes a switching circuit that receives a first signal on first input terminal and a second signal on a second input terminal and includes set of switches that is configured to apply the first and second signals to the first and second differential amplification circuits such that in a first switching state an amplified voltage difference of the first and second signals is available between the two output terminals, and in a second switching state an amplified current difference of the first and second signals is available between the two output terminals.Type: GrantFiled: August 28, 2014Date of Patent: May 24, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Imai, Shinji Nakatsuka
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Publication number: 20160079924Abstract: According to one embodiment, there are provided a bias voltage generation circuit that generates a bias voltage in an operational amplifier according to a bias current generated inside, and an adaptive timing control circuit that temporarily increases the bias current at a timing at which a first control signal configured to control an input signal of the operational amplifier changes in level.Type: ApplicationFiled: March 11, 2015Publication date: March 17, 2016Inventors: Yosuke Ogawa, Shigeo Imai, Shinji Nakatsuka
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Publication number: 20150236661Abstract: According to one embodiment, an amplification circuit includes first and second differential amplification circuits, each having an output connected to an output terminal and a feedback resistor connected between the output and a negative input of the respective differential amplification circuit. The amplification circuit includes a switching circuit that receives a first signal on first input terminal and a second signal on a second input terminal and includes set of switches that is configured to apply the first and second signals to the first and second differential amplification circuits such that in a first switching state an amplified voltage difference of the first and second signals is available between the two output terminals, and in a second switching state an amplified current difference of the first and second signals is available between the two output terminals.Type: ApplicationFiled: August 28, 2014Publication date: August 20, 2015Inventors: Shigeo IMAI, Shinji NAKATSUKA
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Patent number: 8526339Abstract: An echo cancellation circuit in a full duplex two-way communication system comprising: an input/output terminal; a subtractor having a positive and a negative input terminals, in which a first transmission signal is inputted to the negative input terminal as a pseudo echo signal, the first transmission signal is inputted through an output buffer to the positive input terminal as an echo signal, the pseudo echo signal inputted to the negative input terminal is subtracted from the echo signal inputted to the positive input terminal; and a result of the subtraction is outputted; and an echo cancellation error reducing unit having a D/A converter at an input side or an output side of the subtractor.Type: GrantFiled: March 9, 2011Date of Patent: September 3, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Nakatsuka, Kazuhiro Oda
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Publication number: 20110222446Abstract: An echo cancellation circuit in a full duplex two-way communication system comprising: an input/output terminal; a subtractor having a positive and a negative input terminals, in which a first transmission signal is inputted to the negative input terminal as a pseudo echo signal, the first transmission signal is inputted through an output buffer to the positive input terminal as an echo signal, the pseudo echo signal inputted to the negative input terminal is subtracted from the echo signal inputted to the positive input terminal; and a result of the subtraction is outputted; and an echo cancellation error reducing unit having a D/A converter at an input side or an output side of the subtractor.Type: ApplicationFiled: March 9, 2011Publication date: September 15, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Shinji Nakatsuka, Kazuhiro Oda