Abstract: When a PWM signal is generated by PWM generators which are provided for the number of channels, each PWM generator outputs the PWM start schedule data showing the timing of startup of the PWM signal to the CPU. When the number of PWM signals which start at substantially the same time exceeds a predetermined number on the basis of the PWM start schedule data, the CPU outputs delay setting data with respect to a channel corresponding to a portion exceeding the predetermined number to the PWM generator as the one showing that the generation of the PWM signal is to be delayed. The PWM generator delays the PWM signal, when the delay setting data shows a delay. As a result, a multi-channel pulse width modulation apparatus which can prevent a decrease in the operational reliability due to simultaneous start of the pulse width modulation signals can be provided.

Abstract: When a PWM signal is generated by PWM generators which are provided for the number of channels, each PWM generator outputs the PWM start schedule data showing the timing of startup of the PWM signal to the CPU. When the number of PWM signals which start at substantially the same time exceeds a predetermined number on the basis of the PWM start schedule data, the CPU outputs delay setting data with respect to a channel corresponding to a portion exceeding the predetermined number to the PWM generator as the one showing that the generation of the PWM signal is to be delayed. The PWM generator delays the PWM signal, when the delay setting data shows a delay. As a result, a multi-channel pulse width modulation apparatus which can prevent a decrease in the operational reliability due to simultaneous start of the pulse width modulation signals can be provided.

Abstract: To obtain the sufficiently precise result of floating-point accumulation even if the quantity of computation is enormous, a floating-point accumulator according to the present invention is constituted as follows:When two floating-point data are stored in any of shift registers, the two data are respectively output to BUS0 and BUS1 via one connected to the shift register of buffers. The two output data are input to an adder via BUS0 and BUS1 and output as added result data after adding the floating-point numbers. The above added result data is returned to each input of the shift registers via BUSW and a multiplexer and written into the shift register corresponding to the addition of the higher level by one of the shift register holding floating-point data before addition. The floating-point numbers are accumulated by repeating the above operation.

Abstract: A proximal particle list including numbers of particles located within a predetermined distance from a particular particle is generated in calculating a Coulomb force acting on a particular particle or a related potential. A van der Waals force acting on the particular particle or a related potential is thereafter calculated based on only the particles included in the proximal particle list.

Abstract: A device for calculating differences includes a difference circuit for generating difference signals .DELTA.x.sub.j =x.sub.j -x.sub.i, .DELTA.y.sub.j =y.sub.j -y.sub.i, and .DELTA.z.sub.j =z.sub.j -z.sub.i between coordinates of i having (x.sub.i, y.sub.i, z.sub.i) coordinate signals and coordinates of j having (x.sub.j, y.sub.j, z.sub.j) coordinate signals in an orthogonal coordinate system. The difference circuit includes an x-axis circuit, responsive to the x.sub.i and x.sub.j signals having a first circuit for receiving the x.sub.i coordinate signal and the x.sub.j coordinate signal and generating the .DELTA.x.sub.j ; a comparison circuit for comparing the x.sub.i and x.sub.j signals and determining whether the .DELTA.x.sub.j is less than a first set value -L.sub.x /2 corresponding to a length of a side of a virtual rectangular parallelepiped or greater than a second set value L.sub.x /2 corresponding to the length of the side of the virtual rectangular parallelepiped, L.sub.

Abstract: A matrix calculating circuit for calculating with respect to a matrix in which all diagonal elements are equal to one another and the remaining elements are equal to one another. The matrix calculating circuit includes a register for successively latching "n" items of data that are time-sequentially inputted thereto, a delay circuit for delaying the data supplied from the register by "n" clocks, a total-sum calculating unit for calculating a total sum of the "n" items of data supplied from the register, a data latch for latching a value of the total-sum calculating unit, and an adder for adding output data of the delay circuit to output data of the data latch. The "n" items of data to be latched by the register may be supplied from an output portion of an image sensor, to remove the influence due to the crosstalk.

Abstract: A halftone image generating apparatus for use in a halftone image generating system for generating threshold value data corresponding to positions in a main scanning direction and a subsidiary scanning direction, comprising a threshold value data generating circuit for generating the threshold value data in a matrix pattern having a variable number of lines and rows, and for converting input picture image data having chromatic gradations into binary value data by comparing the input picture image data to the threshold value data, and a circuit for forming a scanning mesh dot image corresponding to the input picture image data.

Abstract: This pipeline processor has an ALU, an accumulator register, a first data bus connected through a first switch circuit to output terminals of the accumulator register, and a second data bus connected to input terminals of the accumulator register through a second switch circuit. Data on the first data base is processed by the ALU, and supplied through a third switch circuit to the second data bus. First to third switch circuits respectively receive first to third control signals generated at a predetermined timing for controlling the data transfer by the signal generator of an execution control circuit. The execution control circuit is further provided with signal generator for generating a fourth control signal which renders the second switch circuit conductive during the precharge period of the first and second data buses. The third and fourth control signals are supplied through an OR gate to the second switch circuit.

Abstract: A mode setting control system comprising a one-chip microprocessor and a mode setting circuit provided outside the microprocessor. The mode setting circuit comprises mode designating switches, diodes and a flip-flop. Data representing the mode designated by the switches is written into the one-chip microprocessor through I/O pins. After the one-chip microprocessor has been brought out of the reset state, an ADR signal is supplied from the one-chip microprocessor through an ADR pin thereof, whichever operation mode the microprocessor is set to. The ADR signal is supplied to the mode setting circuit, thus electrically disconnecting the same from the one-chip microprocessor. Consequently, data other than the mode data can be written into the I/O pins.

Abstract: A main power source voltage is compared with a reference voltage, when the main power voltage drops lower than the reference voltage, an operation/halt signal is formed, a read/write memory write inhibit signal is formed in response to the operation/halt signal, and the read/write memory is inhibited in operation. This write inhibit signal is formed by setting a D-type latch at the timing of the transition of the NIF signal to active mode.