Patents by Inventor Shinjiro Yamada

Shinjiro Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240033567
    Abstract: Provided is an instrument and a training method capable of promoting muscle stretching and increasing a range of motion of a joint. An instrument according to the present invention is an instrument for reducing muscle pain during muscle stretching and increasing a range of motion of a joint, including: a main body portion; and a pressing portion that is provided to protrude from the main body portion and presses to stimulate a Pacinian corpuscle present in a palm of a user, in which by grasping the main body portion with one hand, the pressing portion accurately contacts the Pacinian corpuscle, and an appropriate pressure can be applied to the Pacinian corpuscle.
    Type: Application
    Filed: December 3, 2021
    Publication date: February 1, 2024
    Inventors: Hisayo SUGAO, Shinjiro YAMADA
  • Publication number: 20230225260
    Abstract: To provide a mechanism for performing environment control in a plant cultivation device and process control regarding to a work process for cultivating a plant. A plant cultivation device includes a plurality of sensors for monitoring a growing condition of a plant to be cultivated; an environment controlling unit for controlling an environment which is a condition of at least one of light, air, water, and space in the plant cultivation device; and a process controlling unit for controlling a work process for cultivating the plant.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 20, 2023
    Inventors: Kazutaka OHSHIMA, Shinjiro YAMADA, Takuji AKIYAMA, Shunsuke SAKAGUCHI, Kosuke YAMADA
  • Publication number: 20210185955
    Abstract: The purpose of the present invention is to reduce location-related and time-related changes in a cultivation environment in a plant factory. This cultivation device 1A is used in an artificial light plant factory, and is provided with: a closed cultivation room 10A; a plurality of cultivation chambers 20A defined by dividing the cultivation room 10A in the vertical direction; an air circulation device 30 which supplies air adjusted to a predetermined condition to each of the plurality of cultivation chambers 20A at a predetermined flow rate and collects the supplied air from the plurality of cultivation chambers 20A to circulate the air; and a nutrient solution circulation device 40 which supplies a nutrient solution adjusted to a predetermined condition to each of the plurality of cultivation chambers 20A at a predetermined flow rate and collects the supplied nutrient solution from the plurality of cultivation chambers 20A to circulate the nutrient solution.
    Type: Application
    Filed: April 12, 2019
    Publication date: June 24, 2021
    Inventors: Shunsuke Sakaguchi, Takuji Akiyama, Kazutaka Ohshima, Kosuke Yamada, Shinjiro Yamada
  • Patent number: 8458508
    Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: June 4, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Misaka, Shinjiro Yamada
  • Publication number: 20110029802
    Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.
    Type: Application
    Filed: October 8, 2010
    Publication date: February 3, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Misaka, Shinjiro Yamada
  • Patent number: 7836325
    Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: November 16, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Misaka, Shinjiro Yamada
  • Publication number: 20090119670
    Abstract: Disclosed is a method of constructing and executing a process. A conventional process is minutely divided into minimum unit subprocesses, and the minutely divided subprocesses are classified into a decision subprocesses and a routine subprocess by whether they require decision-making. Any subprocess which is executable using the setup condition in a specific decision subprocess is classified into the routine subprocess in such a manner that the classified routine subprocess follows on the specific decision subprocess. One or a series of decision subprocesses are combined with one or a series of routine subprocesses which are executable on the condition of the completion of the decision subprocesses to form one unit process, and a job-support computer program is created to allow the plurality of subprocesses included in the one unit process to be successively executed.
    Type: Application
    Filed: July 2, 2008
    Publication date: May 7, 2009
    Applicant: INCS, Inc.
    Inventors: Shinjiro Yamada, Masayuki Nakao, Tomohito Ohmori, Michiyo Kuwabara
  • Patent number: 7409686
    Abstract: Disclosed is a method of constructing and executing a process. A conventional process is minutely divided into minimum unit subprocesses, and the minutely divided subprocesses are classified into a decision subprocesses and a routine subprocess by whether they require decision-making. Any subprocess which is executable using the setup condition in a specific decision subprocess is classified into the routine subprocess in such a manner that the classified routine subprocess follows on the specific decision subprocess. One or a series of decision subprocesses are combined with one or a series of routine subprocesses which are executable on the condition of the completion of the decision subprocesses to form one unit process, and a job-support computer program is created to allow the plurality of subprocesses included in the one unit process to be successively executed.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: August 5, 2008
    Assignee: INCS, Inc.
    Inventors: Shinjiro Yamada, Masayuki Nakao, Tomohito Ohmori, Michiyo Kuwabara
  • Patent number: 7356375
    Abstract: A manufacturing process control apparatus that controls a manufacturing process divided into a plurality of steps that are controlled by a plurality of user terminals, comprising transmitting means that, when conditions for the execution of one step of said plurality of steps are met, transmits to the user terminal that controls said one step information to the effect that said step can be started, and receiving means that, when said one step of the plurality of steps is complete, receives from the user terminal that controls said one step information to the effect that said one step is complete.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: April 8, 2008
    Assignee: INCS Inc.
    Inventors: Shinjiro Yamada, Seiki Sato, Katsunori Shimomura, Tomohito Ohmori, Michiyo Kuwabara, Keiji Okamoto, Katsuji Iwasaki, Hidenori Sasaki
  • Publication number: 20070271479
    Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.
    Type: Application
    Filed: July 27, 2007
    Publication date: November 22, 2007
    Inventors: Satoshi Misaka, Shinjiro Yamada
  • Patent number: 7269677
    Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: September 11, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Misaka, Shinjiro Yamada
  • Publication number: 20070027563
    Abstract: A manufacturing process control apparatus that controls a manufacturing process divided into a plurality of steps that are controlled by a plurality of user terminals, comprising transmitting means that, when conditions for the execution of one step of said plurality of steps are met, transmits to the user terminal that controls said one step information to the effect that said step can be started, and receiving means that, when said one step of the plurality of steps is complete, receives from the user terminal that controls said one step information to the effect that said one step is complete.
    Type: Application
    Filed: October 6, 2006
    Publication date: February 1, 2007
    Inventors: Shinjiro Yamada, Seiki Sato, Katsunori Shimomura, Tomohito Ohmori, Michiyo Kuwabara, Keiji Okamoto, Katsuji Iwasaki, Hidenori Sasaki
  • Patent number: 7120510
    Abstract: A method of executing a plurality of steps that are performed sequentially in temporal order under computer control. Each of the plurality of steps is executed by one of a plurality of terminal computers. When a terminal computer assigned to a step has completed the work in the step and is able to execute the work in the next step, it sends a work completion signal to a central processing computer. The central processing computer receives this work completion signal and prepares a work item notice that indicates that the next step can be started, such that the notice can be displayed on the screen of the terminal computer used for the next step. The terminal computer used for the next step allows the notice displayed on its screen to be clicked to start work on the next step assigned to it.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: October 10, 2006
    Assignee: INCS Inc.
    Inventors: Shinjiro Yamada, Seiki Sato, Katsunori Shimomura, Tomohito Ohmori, Michiyo Kuwabara, Keiji Okamoto, Katsuji Iwasaki, Hidenori Sasaki
  • Publication number: 20050085927
    Abstract: A method of executing a plurality of steps that are performed sequentially in temporal order under computer control is provided wherein a central processing computer and a plurality of terminal computers are provided. Each of the plurality of steps is executed by one of the terminal computers. When one of the terminal computers assigned to a single step has completed the work in the step assigned to it and is able to execute the work in the next step, that terminal computer sends a work completion signal to the central processing computer. The central processing computer receives this work completion signal and prepares a work item notice that indicates that the next step can be started, such that the notice can be displayed on the screen of the terminal computer used for the next step. The terminal computer used for the next step allows the work item notice displayed on its display screen to be clicked to start work on the next step assigned to it.
    Type: Application
    Filed: October 27, 2004
    Publication date: April 21, 2005
    Inventors: Shinjiro Yamada, Seiki Sato, Katsunori Shimomura, Tomohito Ohmori, Michiyo Kuwabara, Keiji Okamoto, Katsuji Iwasaki, Hidenori Sasaki
  • Patent number: 6871109
    Abstract: The present invention provides a die design support method and system capable of reducing the time-period required for a die design, allowing an unskilled die engineer to perform a die design without difficulties, and coping with a product design change in a short time-period. A standard die design procedure is stored as “master die data” in advance using a function of a CAD system or the like. When a product design data is entered, the design procedure is automatically executed to the design data in accordance with the stored master die data. Preferably, the entire master die data is divided into a plurality of processes, such as a process of creating a scaling model, and a process of creating a parting model.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: March 22, 2005
    Assignee: INCS, Inc.
    Inventors: Shinjiro Yamada, Seiki Sato, Atsuo Suzuki, Takao Ikeda, Katsuji Iwasaki, Daichi Ninagawa, Kazuhiro Kuwahara, Junya Uramoto, Atsushi Miyadera, Atsushi Sakurai
  • Patent number: 6823227
    Abstract: A method of executing a plurality of steps that are performed sequentially in temporal order under computer control is provided wherein a central processing computer and a plurality of terminal computers are provided. Each of the plurality of steps is executed by one of the terminal computers. When one of the terminal computers assigned to a single step has completed the work in the step assigned to it and is able to execute the work in the next step, that terminal computer sends a work completion signal to the central processing computer. The central processing computer receives this work completion signal and prepares a work item notice that indicates that the next step can be started, such that the notice can be displayed on the screen of the terminal computer used for the next step. The terminal computer used for the next step allows the work item notice displayed on its display screen to be clicked to start work on the next step assigned to it.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: November 23, 2004
    Assignee: INCS Inc.
    Inventors: Shinjiro Yamada, Seiki Sato, Katsunori Shimomura, Tomohito Ohmori, Michiyo Kuwabara, Keiji Okamoto, Katsuji Iwasaki, Hidenori Sasaki
  • Publication number: 20040193298
    Abstract: The present invention provides a die design support method and system capable of reducing the time-period required for a die design, allowing an unskilled die engineer to perform a die design without difficulties, and coping with a product design change in a short time-period. A standard die design procedure is stored as “master die data” in advance using a function of a CAD system or the like. When a product design data is entered, the design procedure is automatically executed to the design data in accordance with the stored master die data. Preferably, the entire master die data is divided into a plurality of processes, such as a process of creating a scaling model, and a process of creating a parting model.
    Type: Application
    Filed: March 26, 2003
    Publication date: September 30, 2004
    Inventors: Shinjiro Yamada, Seiki Sato, Atsuo Suzuki, Takao Ikeda, Katsuji Iwasaki, Daichi Ninagawa, Kazuhiro Kuwahara, Junya Uramoto, Atsushi Miyadera, Atsushi Sakurai
  • Publication number: 20040153839
    Abstract: An information processing device which features low power consumption without deterioration in interruption request response speed. It specifies a waiting time until execution of a given event and makes a system call. It comprises: a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor capable of storing the waiting time upon the system call; and a first cycle supervisor capable of storing a time until the next interruption request from the first timer circuit. The timeout supervisor stores the time calculated by subtraction of the time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.
    Type: Application
    Filed: October 29, 2003
    Publication date: August 5, 2004
    Inventors: Satoshi Misaka, Shinjiro Yamada
  • Publication number: 20040049487
    Abstract: Disclosed is a method of constructing and executing a process. A conventional process is minutely divided into minimum unit subprocesses, and the minutely divided subprocesses are classified into a decision subprocesses and a routine subprocess by whether they require decision-making. Any subprocess which is executable using the setup condition in a specific decision subprocess is classified into the routine subprocess in such a manner that the classified routine subprocess follows on the specific decision subprocess. One or a series of decision subprocesses are combined with one or a series of routine subprocesses which are executable on the condition of the completion of the decision subprocesses to form one unit process, and a job-support computer program is created to allow the plurality of subprocesses included in the one unit process to be successively executed.
    Type: Application
    Filed: August 13, 2003
    Publication date: March 11, 2004
    Applicant: INCS INC.
    Inventors: Shinjiro Yamada, Masayuki Nakao, Tomohito Ohmori, Michiyo Kuwabara
  • Publication number: 20030065412
    Abstract: A method of executing a plurality of steps that are performed sequentially in temporal order under computer control is provided wherein a central processing computer and a plurality of terminal computers are provided. Each of the plurality of steps is executed by one of the terminal computers. When one of the terminal computers assigned to a single step has completed the work in the step assigned to it and is able to execute the work in the next step, that terminal computer sends a work completion signal to the central processing computer. The central processing computer receives this work completion signal and prepares a work item notice that indicates that the next step can be started, such that the notice can be displayed on the screen of the terminal computer used for the next step. The terminal computer used for the next step allows the work item notice displayed on its display screen to be clicked to start work on the next step assigned to it.
    Type: Application
    Filed: November 12, 2002
    Publication date: April 3, 2003
    Applicant: INCS Inc.
    Inventors: Shinjiro Yamada, Seiki Sato, Katsunori Shimomura, Tomohito Ohmori, Michiyo Kuwabara, Keiji Okamoto, Katsuji Iwasaki, Hidenori Sasaki