Patents by Inventor Shinken Okamoto
Shinken Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10606481Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: GrantFiled: August 10, 2018Date of Patent: March 31, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Shinken Okamoto
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Publication number: 20190004706Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: ApplicationFiled: August 10, 2018Publication date: January 3, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Shinken OKAMOTO
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Patent number: 10073624Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: GrantFiled: January 10, 2017Date of Patent: September 11, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Shinken Okamoto
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Publication number: 20170123673Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: ApplicationFiled: January 10, 2017Publication date: May 4, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Shinken OKAMOTO
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Patent number: 9569111Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: GrantFiled: April 22, 2016Date of Patent: February 14, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Shinken Okamoto
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Publication number: 20160239214Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: ApplicationFiled: April 22, 2016Publication date: August 18, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Shinken OKAMOTO
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Patent number: 9348699Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: GrantFiled: April 2, 2015Date of Patent: May 24, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Shinken Okamoto
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Publication number: 20150212888Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: ApplicationFiled: April 2, 2015Publication date: July 30, 2015Applicant: Kabushiki Kaisha ToshibaInventor: Shinken OKAMOTO
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Patent number: 9053016Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: GrantFiled: June 10, 2014Date of Patent: June 9, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Shinken Okamoto
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Publication number: 20140297930Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: ApplicationFiled: June 10, 2014Publication date: October 2, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Shinken OKAMOTO
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Publication number: 20140059281Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: ApplicationFiled: November 1, 2013Publication date: February 27, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Shinken OKAMOTO
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Patent number: 8605504Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: GrantFiled: September 20, 2010Date of Patent: December 10, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Shinken Okamoto
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Publication number: 20110197045Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.Type: ApplicationFiled: September 20, 2010Publication date: August 11, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Shinken OKAMOTO
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Patent number: 6993690Abstract: A processing unit 12 that is provided in a memory unit 10 can transfer information that is stored in a corresponding address to a spare memory area and prohibit writing of information into the corresponding address when the number write operations to the respective addresses of flash memories 11-1 through 11-3 reaches a set number or when the error frequency in the information stored in the respective addresses reaches a set frequency. When the remaining capacity of a spare memory area reaches a set capacity, an indication lamp 14 may lit or a memory status signal may be transmitted to a processing unit 21 of a computer 20 and displayed on a display unit 30. The memory processing unit 12 may lit the indication lamp 14 when the number write operations to the respective addresses of flash memories 11-1 through 11-3 reaches a set number or when the error frequency in the information stored in the respective addresses reaches a set frequency.Type: GrantFiled: July 23, 1999Date of Patent: January 31, 2006Assignee: Hagiwara Sys-Com Co., Ltd.Inventor: Shinken Okamoto