Patents by Inventor Shinkichi Hotta

Shinkichi Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5247521
    Abstract: In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.
    Type: Grant
    Filed: March 9, 1992
    Date of Patent: September 21, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Yasushi Akao, Shinkichi Hotta, Haruo Keida
  • Patent number: 5142536
    Abstract: In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.
    Type: Grant
    Filed: September 19, 1990
    Date of Patent: August 25, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Yasushi Akao, Shinkichi Hotta, Haruo Keida
  • Patent number: 4989208
    Abstract: In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.
    Type: Grant
    Filed: April 20, 1987
    Date of Patent: January 29, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Yasushi Akao, Shinkichi Hotta, Haruo Keida
  • Patent number: 4074262
    Abstract: A key input circuit includes a binary-coded N-ary counter consisting of a plurality of binary counters, a decoder decoding coded pulse outputs of the counter for converting the counter outputs into a plurality of timing pulse signals, which are applied respectively to a plurality of keys. These timing pulse signals form a key information input by manipulation of the corresponding key, and a plurality of gates are provided for coding the key information by gating the input provided by the specific coded pulse output of the counter in response to receipt of the control input provided by the specific key signal applied through the manipulated key.
    Type: Grant
    Filed: January 27, 1976
    Date of Patent: February 14, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Kosei Nomiya, Shinkichi Hotta
  • Patent number: 4037212
    Abstract: In an information processing system controlled systematically by a programable logic array, the initialization of the contents of a predetermined memory circuit after switching-on the power is effected by setting the contents of the memory circuit to an initial value by means of a signal generated automatically or manually.
    Type: Grant
    Filed: January 20, 1976
    Date of Patent: July 19, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Kosei Nomiya, Takao Tsuiki, Takeshi Kobayashi, Shinkichi Hotta