Patents by Inventor Shinobu Sumi

Shinobu Sumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11086160
    Abstract: A light control device including a light control sheet including light control units each reversibly change light transmittance and positioned according to a first arrangement that has a regularity, a detection sheet including detection units each detect external input and positioned according to a second arrangement that has a regularity same as the regularity of the first arrangement, a driving unit that outputs to each of the light control units a change signal for changing light transmittance, and a light control processing unit which associates each of the detection units with at least one of the light control units, and causes the driving unit to output the change signal to the light control unit associated with the detection unit that has detected the external input.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: August 10, 2021
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Masanori Sakamoto, Shinobu Sumi, Wataru Ookubo
  • Publication number: 20190258103
    Abstract: A light control device including a light control sheet including light control units each reversibly change light transmittance and positioned according to a first arrangement that has a regularity, a detection sheet including detection units each detect external input and positioned according to a second arrangement that has a regularity same as the regularity of the first arrangement, a driving unit that outputs to each of the light control units a change signal for changing light transmittance, and a light control processing unit which associates each of the detection units with at least one of the light control units, and causes the driving unit to output the change signal to the light control unit associated with the detection unit that has detected the external input.
    Type: Application
    Filed: April 1, 2019
    Publication date: August 22, 2019
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Masanori SAKAMOTO, Shinobu Sumi, Wataru Ookubo
  • Patent number: 8227906
    Abstract: An image processor by way of a transistor array in which a plurality of transistors are formed on a substrate comprising a plurality of polysilicon thin-film transistors using a first semiconductor layer composed of polysilicon formed on the substrate and functional devices having a plurality of amorphous silicon thin-film transistors using a second semiconductor layer composed of amorphous silicon which are formed in an upper layer more superior than the first semiconductor layer. The polysilicon thin-film transistors and functional devices include a plurality of electrode layers composed of a conductor layer, for instance, the functional devices at least of any one of the electrode layers are formed in the same layer as any one the electrode layers of the polysilicon thin-film transistors.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: July 24, 2012
    Assignee: Casio Computer Co., Ltd.
    Inventors: Kazuhiro Sasaki, Hiroshi Matsumoto, Shinobu Sumi
  • Publication number: 20110169843
    Abstract: An image processor by way of a transistor array in which a plurality of transistors are formed on a substrate comprising a plurality of polysilicon thin-film transistors using a first semiconductor layer composed of polysilicon formed on the substrate and functional devices having a plurality of amorphous silicon thin-film transistors using a second semiconductor layer composed of amorphous silicon which are formed in an upper layer more superior than the first semiconductor layer. The polysilicon thin-film transistors and functional devices include a plurality of electrode layers composed of a conductor layer, for instance, the functional devices at least of any one of the electrode layers are formed in the same layer as any one the electrode layers of the polysilicon thin-film transistors.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 14, 2011
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Kazuhiro Sasaki, Hiroshi Matsumoto, Shinobu Sumi
  • Patent number: 7915723
    Abstract: An image processor by way of a transistor array in which a plurality of transistors are formed on a substrate comprising a plurality of polysilicon thin-film transistors using a first semiconductor layer composed of polysilicon formed on the substrate and functional devices having a plurality of amorphous silicon thin-film transistors using a second semiconductor layer composed of amorphous silicon which are formed in an upper layer more superior than the first semiconductor layer. The polysilicon thin-film transistors and functional devices include a plurality of electrode layers composed of a conductor layer, for instance, the functional devices at least of any one of the electrode layers are formed in the same layer as any one the electrode layers of the polysilicon thin-film transistors.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: March 29, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventors: Kazuhiro Sasaki, Hiroshi Matsumoto, Shinobu Sumi
  • Patent number: 7851738
    Abstract: A driver circuit provided with a shift signal generator for sequentially outputting shift signals at a predetermined time interval; a plurality of amplifiers respectively receiving a plurality of detection signals read out in parallel corresponding to a detectable object image pattern and respectively receiving the shift signals, wherein the plurality of amplifiers respectively amplify and output the detection signals inputted thereto based on the output timing of each of the shift signals inputted thereto; a data converter for outputting in time series each of the amplified detection signals outputted from each of the amplifiers based on the output timing of each of the shift signals and for generating time series read data. Power consumption and the amount of heat generation are suppressed in the driver circuit provided with means to individually control a supply state of electrical current to each of the amplifiers.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: December 14, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventor: Shinobu Sumi
  • Patent number: 7671326
    Abstract: Disclosed is an image inputting apparatus including: a base; a sensor main body coupled with the base so as to be able to move in a vertical direction on the base; a switch provided on either one of an upper surface side of the base or a lower surface side of the sensor main body; and a convex part provided on another one of the upper surface side of the base or the lower surface side of the sensor main body at a position facing to the switch.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: March 2, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shinobu Sumi, Takafumi Ohashi, Yasushi Mizutani, Kazuhiro Sasaki
  • Publication number: 20080265186
    Abstract: Disclosed is an image inputting apparatus including: a base; a sensor main body coupled with the base so as to be able to move in a vertical direction on the base; a switch provided on either one of an upper surface side of the base or a lower surface side of the sensor main body; and a convex part provided on another one of the upper surface side of the base or the lower surface side of the sensor main body at a position facing to the switch.
    Type: Application
    Filed: April 22, 2008
    Publication date: October 30, 2008
    Applicant: Casio Computer Co., Ltd.
    Inventors: Shinobu Sumi, Takafumi Ohashi, Yasushi Mizutani, Kazuhiro Sasaki
  • Patent number: 7180356
    Abstract: The level shift circuit in the semiconductor circuit of the invention has a configuration comprising an input stage inverter circuit which inputs an input signal having a first voltage amplitude and outputs an inverted signal of this input signal, an output stage inverter circuit which inputs at least the output signal of the input stage inverter circuit and the output signal has a second voltage amplitude larger than the first voltage amplitude and a bootstrap circuit section which boosts a voltage value of input signal voltage of the output stage inverter circuit and the potential difference of the input signal and the output signal is held as a voltage component. The level shift circuit of each circuit is a Thin-Film Transistor at least using a semiconductor layer composed of amorphous silicon having single channel polarity as a switching element.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: February 20, 2007
    Assignee: Casio Computer Co., Ltd.
    Inventors: Minoru Kanbara, Shinobu Sumi, Takumi Yamamoto
  • Publication number: 20060140076
    Abstract: A driver circuit provided with a shift signal generator for sequentially outputting shift signals at a predetermined time interval; a plurality of amplifiers respectively receiving a plurality of detection signals read out in parallel corresponding to a detectable object image pattern and respectively receiving the shift signals, wherein the plurality of amplifiers respectively amplify and output the detection signals inputted thereto based on the output timing of each of the shift signals inputted thereto; a data converter for outputting in time series each of the amplified detection signals outputted from each of the amplifiers based on the output timing of each of the shift signals and for generating time series read data. Power consumption and the amount of heat generation are suppressed in the driver circuit provided with means to individually control a supply state of electrical current to each of the amplifiers.
    Type: Application
    Filed: December 27, 2005
    Publication date: June 29, 2006
    Applicant: Casio Computer Co., Ltd.
    Inventor: Shinobu Sumi
  • Publication number: 20050176194
    Abstract: An image processor by way of a transistor array in which a plurality of transistors are formed on a substrate comprising a plurality of polysilicon thin-film transistors using a first semiconductor layer composed of polysilicon formed on the substrate and functional devices having a plurality of amorphous silicon thin-film transistors using a second semiconductor layer composed of amorphous silicon which are formed in an upper layer more superior than the first semiconductor layer. The polysilicon thin-film transistors and functional devices include a plurality of electrode layers composed of a conductor layer, for instance, the functional devices at least of any one of the electrode layers are formed in the same layer as any one the electrode layers of the polysilicon thin-film transistors.
    Type: Application
    Filed: January 28, 2005
    Publication date: August 11, 2005
    Applicant: Casio Computer Co., Ltd.
    Inventors: Kazuhiro Sasaki, Hiroshi Matsumoto, Shinobu Sumi
  • Publication number: 20050156844
    Abstract: The level shift circuit in the semiconductor circuit of the invention has a configuration comprising an input stage inverter circuit which inputs an input signal having a first voltage amplitude and outputs an inverted signal of this input signal, an output stage inverter circuit which inputs at least the output signal of the input stage inverter circuit and the output signal has a second voltage amplitude larger than the first voltage amplitude and a bootstrap circuit section which boosts a voltage value of input signal voltage of the output stage inverter circuit and the potential difference of the input signal and the output signal is held as a voltage component. The level shift circuit of each circuit is a Thin-Film Transistor at least using a semiconductor layer composed of amorphous silicon having single channel polarity as a switching element.
    Type: Application
    Filed: December 20, 2004
    Publication date: July 21, 2005
    Applicant: Casio Computer Co., Ltd.
    Inventors: Minoru Kanbara, Shinobu Sumi, Takumi Yamamoto
  • Patent number: 6859231
    Abstract: In a photosensor system formed of a photosensor array including a plurality of photosensors arranged in a two dimensional direction, the intervals of the reset pulse, read pulse and pre-charge pulse applied to each row of the photosensor array are respectively set equal to the sum of the reset period, the read period, and the pre-charge period. It follows that even where the read processing time of a single screen is shortened by allowing the processing cycles for the rows to partially overlap with each other, the reset period, the pre-charge period and the read period are prevented from being overlapped in time with each other, making it possible to perform the read operation accurately.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: February 22, 2005
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shinobu Sumi, Yoshiaki Nakamura
  • Publication number: 20040239668
    Abstract: A display device for displaying images corresponding to digital signals information comprising a display panel with a plurality of display pixels arranged in matrix form near the intersecting points of a plurality of scanning lines and a plurality of signal lines which intersect perpendicularly with each other; a scanning driver circuit for sequentially applying scanning signals; a signal driver circuit comprising a plurality of gradation current generation supply circuit sections comprising a module current generation circuit which generates a plurality of module currents corresponding to each digital signal bit based on reference voltage; a gradation current generation circuit which integrates selectively each of the module currents, generates gradation currents and supplies each of a plurality of the signal lines; a reference voltage generation circuit which applies in common the reference voltage to a plurality of the gradation current generation circuits sections.
    Type: Application
    Filed: May 26, 2004
    Publication date: December 2, 2004
    Applicant: Casio Computer Co., Ltd.
    Inventors: Katsuhiko Morosawa, Hiromitsu Ishii, Tomoyuki Shirasaki, Shinobu Sumi
  • Patent number: 6323623
    Abstract: The present invention relates to a charging device for storing electric energy in a plurality of electrical double layer capacitors, comprising a power source circuit, a capacitor bank having a plurality of capacitors, a control circuit for switching an interconnection state of the plurality of capacitors, and a voltage monitor circuit for monitoring a charged voltage in the plurality of capacitors, which repetitively carries out a step of performing a charging operation by switching the plurality of capacitors in the capacitor bank to a serial connection state, and a step of monitoring a charged voltage by using a voltage monitor circuit by switching the plurality of capacitors to a parallel connection state until the charged voltage reaches a predetermined value.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: November 27, 2001
    Assignee: Casio Computer Co., Ltd.
    Inventors: Kaoru Someya, Shinobu Sumi
  • Patent number: 6169532
    Abstract: A display apparatus comprises a liquid crystal display panel, gate driver circuit for scanning gate lines of the display panel, drain driver circuit for supplying the display data to drain lines of the display panel, level modulator circuit coupled to the display panel and control circuit. The control circuit determines that video data represents a still image data, stoped the operation of the drain driver circuit and activates the level modulator circuit. The level modulator circuit reads out from display signals from the display panel and re-writes display signals to the display panel in order to display the still image on the display panel. In this manner, the electric power consumed by the drain circuit can be conserved when the display apparatus displays the still image.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: January 2, 2001
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shinobu Sumi, Minoru Kanbara