Abstract: A PLL frequency synthesizer has a detecting circuit 7 integrating a difference of an up signal and a down signal down, and outputting a control signal Vg according to the difference, and a charge circuit 5 receiving the control signal Vg, up signal and down signal, charging an output node by a first current ability when the control signal Vg is at a high level and the up signal and the down signal are at high level and at low level, respectively, discharging the output node by first current ability when the control signal Vg is at high level and the up signal and the down signal are at low level and at high level, respectively, charging the output node by second current ability lower than first current ability when the control signal Vg is at high level and the up signal and the down signal are at high level and at low level, respectively, and discharging the output node by second current ability when the control signal is at low level and the up signal and the down signal are at low level and high level.

Abstract: According to an output from a voltage-controlled oscillator, there are generated by a fractional divider a high-frequency division signal and a low-frequency division number. A phase comparison is conducted between the high-frequency division signal and a high-frequency reference signal by a phase comparator. A phase comparison is carried out between the low-frequency division signal and a low-frequency reference signal by a phase comparator. Either one of the outputs from the phase comparators is selected by a selector to be fed to a filter, thereby producing a control voltage for the voltage-controlled oscillator. A high-resolution division is achieved by the fractional division; consequently, disturbance of the oscillation frequency due to a change-over of the selector is suppressed. There is obtained a PLL frequency synthesizer developing a high-speed lock-up and a highly stable oscillation.

Abstract: A transistor circuit has a first and a second transistor differentially connected with each other and having bases receiving an input signal therebetween; a first and a second resistor respectively connected between collectors of the first and second transistors and a first power supply terminal; a third transistor having an emitter receiving a voltage dropped by the first resistor and a collector connected to an output terminal; a fourth transistor having an emitter receiving a voltage dropped by the second resistor; and a fifth transistor having a collector connected to the output terminal and an emitter connected to the second power supply terminal.

Abstract: A circuit for detecting a lock of a phase locked loop comprising a phase comparator receiving a first signal and a second signal for generating a phase difference signal, a waveform shaping circuit connected to receive the phase difference signal for generating an output signal when the phase difference signal indicates a phase difference exceeding a predetermined value, and a multi-stage counter having a frequency division function and having a reset input connected to receive the output signal of the waveform shaping circuit. An input control circuit is connected to receive the first signal and an output of the multi-stage counter and has an output connected to an input of the multi-stage counter for allowing the first signal to be applied to the multi-stage counter only when the output of the multi-stage counter is at a predetermined logic level. The output of the counter provides an lock output.