Patents by Inventor Shinsaku Kubo

Shinsaku Kubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9224919
    Abstract: According to one embodiment, the second insulating film is provided between the first interconnect portion and the second interconnect portion, and at an outer periphery of a side face of the semiconductor layer. The optical layer is provided on the first side and on the second insulating film at the outer periphery. The optical layer is transmissive with respect to light emitted from the light emitting layer. A plurality of protrusions and a plurality of recesses are provided at the first side. Peaks of the protrusions are positioned closer to the second side than an end on the second insulating film side of the optical layer at the outer periphery.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Fujimura, Hironori Yamasaki, Tadashi Ono, Shinsaku Kubo, Shinji Nunotani
  • Publication number: 20150280066
    Abstract: According to one embodiment, the second insulating film is provided between the first interconnect portion and the second interconnect portion, and at an outer periphery of a side face of the semiconductor layer. The optical layer is provided on the first side and on the second insulating film at the outer periphery. The optical layer is transmissive with respect to light emitted from the light emitting layer. A plurality of protrusions and a plurality of recesses are provided at the first side. Peaks of the protrusions are positioned closer to the second side than an end on the second insulating film side of the optical layer at the outer periphery.
    Type: Application
    Filed: September 9, 2014
    Publication date: October 1, 2015
    Inventors: Kazuo Fujimura, Hironori Yamasaki, Tadashi Ono, Shinsaku Kubo, Shinji Nunotani
  • Patent number: 7807334
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 ?m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: October 5, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 7435535
    Abstract: A method for forming patterned insulating elements on a substrate includes a plurality of exposure steps of exposing a photosensitive paste provided on the substrate through at least one mask having a predetermined pattern; a developing step of developing the exposed photosensitive paste to form a precursor pattern; and a firing step of firing the precursor pattern to form the patterned insulating elements. This method is applied to a method for forming an electron source and a method for forming an image display device including the electron source.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: October 14, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Yoshimi Uda, Shinsaku Kubo
  • Patent number: 7318996
    Abstract: A method for forming patterned insulating elements on a substrate includes a plurality of exposure steps of exposing a photosensitive paste provided on the substrate through at least one mask having a predetermined pattern; a developing step of developing the exposed photosensitive paste to form a precursor pattern; and a firing step of firing the precursor pattern to form the patterned insulating elements. This method is applied to a method for forming an electron source and a method for forming an image display device including the electron source.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: January 15, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Yoshimi Uda, Shinsaku Kubo
  • Patent number: 7264842
    Abstract: A manufacturing method for a wiring substrate for a display panel having a plurality of wiring electrodes thereon includes the step of forming wirings in an orthogonal projection area of an image forming member onto the wiring substrate by photolithography using a photo paste. In addition, wires are formed in an area where the frame member is disposed by pattern printing using paste ink for printing.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: September 4, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Patent number: 7211943
    Abstract: A covering layer for insulating between column wirings and device electrodes is formed in a region including each cross point of the column wirings and row wirings and under the column wirings. Thus, when an electron source plate in which a large number of electron-emitting devices are wired in passive matrix is formed, a defect resulting from an interaction between the device electrodes and the column wirings at the time of wiring formation is reduced to improve insulation reliability. Therefore, a high quality image is obtained by a large size and higher density pixel arrangement in an image-forming apparatus using the electron source plate.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: May 1, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Publication number: 20060194156
    Abstract: A method for forming patterned insulating elements on a substrate includes a plurality of exposure steps of exposing a photosensitive paste provided on the substrate through at least one mask having a predetermined pattern; a developing step of developing the exposed photosensitive paste to form a precursor pattern; and a firing step of firing the precursor pattern to form the patterned insulating elements. This method is applied to a method for forming an electron source and a method for forming an image display device including the electron source.
    Type: Application
    Filed: May 2, 2006
    Publication date: August 31, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Yoshimi Uda, Shinsaku Kubo
  • Patent number: 7052823
    Abstract: A method of manufacturing an electroconductive film subject to edge curl due to volume contraction after baking includes sequentially repeating a film-forming step of forming a film containing a photosensitive material and an electroconductive material therein and an exposure step of irradiating a light onto a desired region of the film for a plurality of times to laminate the films. The latent images of the respective layers are integrated. The resulting latent image is developed by removing a non-latent image region of the laminate film after the laminate film is formed. Finally, the developed image is baked. The sequential repetition of the film-forming step and the exposure step act to counteract edge curl formed by volume contraction after baking.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: May 30, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 7052825
    Abstract: A substrate includes fine lines. The fine lines are obtained according to a fine-line forming process, which includes a process of projecting light from above the substrate onto predetermined regions on a photosensitive material provided on the substrate and a developing process after the light projection process. A narrow-width portion is provided at an end portion of each of the fine lines in a longitudinal direction of the fine line. The width of the narrow-width portion is smaller than the width of a portion adjacent to the narrow-width portion.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: May 30, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 7015637
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 ?m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: March 21, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 6962770
    Abstract: In a method of manufacturing an electroconductive film, a developing process is implemented on a photosensitive paste layer (12) having a height of about 13 ?m in a state where exposure is repeated twice in FIG. 1D, and thereafter, a baking process is completed to form a wiring pattern (20). As a result, the curling of an edge formed in the wiring pattern (20) can be remarkably reduced.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: November 8, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20050200267
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 ?m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Application
    Filed: May 12, 2005
    Publication date: September 15, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20050189867
    Abstract: A covering layer for insulating between column wirings and device electrodes is formed in a region including each cross point of the column wirings and row wirings and under the column wirings. Thus, when an electron source plate in which a large number of electron-emitting devices are wired in passive matrix is formed, a defect resulting from an interaction between the device electrodes and the column wirings at the time of wiring formation is reduced to improve insulation reliability. Therefore, a high quality image is obtained by a large size and higher density pixel arrangement in an image-forming apparatus using the electron source plate.
    Type: Application
    Filed: May 2, 2005
    Publication date: September 1, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Patent number: 6903504
    Abstract: A covering layer for insulating between column wirings and device electrodes is formed in a region including each cross point of the column wirings and row wirings and under the column wirings. Thus, when an electron source plate in which a large number of electron-emitting devices are wired in passive matrix is formed, a defect resulting from an interaction between the device electrodes and the column wirings at the time of wiring formation is reduced to improve insulation reliability. Therefore, a high quality image is obtained by a large size and higher density pixel arrangement in an image-forming apparatus using the electron source plate.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: June 7, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Publication number: 20050101051
    Abstract: In a method of manufacturing an electroconductive film, a developing process is implemented on a photosensitive paste layer (12) having a height of about 13 ?m in a state where exposure is repeated twice in FIG. 1D, and thereafter, a baking process is completed to form a wiring pattern (20). As a result, the curling of an edge formed in the wiring pattern (20) can be remarkably reduced.
    Type: Application
    Filed: July 23, 2003
    Publication date: May 12, 2005
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 6866989
    Abstract: A method for forming patterned insulating elements on a substrate includes a plurality of exposure steps of exposing a photosensitive paste provided on the substrate through at least one mask having a predetermined pattern; a developing step of developing the exposed photosensitive paste to form a precursor pattern; and a firing step of firing the precursor pattern to form the patterned insulating elements. This method is applied to a method for forming an electron source and a method for forming an image display device including the electron source.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: March 15, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Yoshimi Uda, Shinsaku Kubo
  • Publication number: 20050019707
    Abstract: A method for forming patterned insulating elements on a substrate includes a plurality of exposure steps of exposing a photosensitive paste provided on the substrate through at least one mask having a predetermined pattern; a developing step of developing the exposed photosensitive paste to form a precursor pattern; and a firing step of firing the precursor pattern to form the patterned insulating elements. This method is applied to a method for forming an electron source and a method for forming an image display device including the electron source.
    Type: Application
    Filed: August 9, 2004
    Publication date: January 27, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Yoshimi Uda, Shinsaku Kubo
  • Publication number: 20040259038
    Abstract: A manufacturing method for a wiring substrate for a display panel having a plurality of wiring electrodes thereon includes the step of forming wirings in an orthogonal projection area of an image forming member onto the wiring substrate by photolithography using a photo paste. In addition, wires are formed in an area where the frame member is disposed by pattern printing using paste ink for printing.
    Type: Application
    Filed: July 9, 2004
    Publication date: December 23, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Patent number: 6787984
    Abstract: A wiring substrate for a display panel having a plurality of wiring electrodes thereon includes an airtight container formed by disposing an opposing substrate through a frame member on the surface of the substrate having the wiring electrodes. The airtight container has an image forming member therein, in which an average angle between a cross section of the wirings and the wiring substrate in an orthogonal projection area of the image forming member onto the wiring substrate is obtuse, while an average angle between a cross section of the wirings and the wiring substrate in an area where the frame member is disposed is acute.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: September 7, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo