Abstract: A niobium-titanium-based oxide includes niobium-titanium-based oxide particles, wherein an Si2p peak area and an Nb3d peak area, as measured by X-ray photoelectron spectroscopy for the niobium-titanium-based oxide particles, satisfy a ratio A of 0.40?A?1.0, provided that the ratio A is the Si2p peak area/the Nb3d peak area.

Abstract: A silicon carbide semiconductor device has an n-type silicon carbide semiconductor substrate, an n-type first semiconductor layer, n-type first JFET regions, a p-type second semiconductor layer, n-type first semiconductor regions, and trenches. The first semiconductor layer has an impurity concentration lower than that of the substrate. The first JFET regions are provided in a surface layer of the first semiconductor layer and have an effective donor concentration higher than that of the first semiconductor. The p-type second semiconductor layer is provided at a surface of the first semiconductor layer. The n-type first semiconductor regions are selectively provided in a surface layer of the second semiconductor layer. The trenches penetrate through the first semiconductor regions, the second semiconductor layer, and the first JFET regions. The first JFET regions are doped with an acceptor that is aluminum and a donor that is nitrogen or phosphorus.

Abstract: A control device causes an air conditioning apparatus to execute a temperature adjustment operation of causing a first temperature to approach a first target temperature at a target time point and causing a second temperature to approach a second target temperature at the target time point. The first temperature is a surface temperature of a partition portion including at least one of a floor, a wall, and a ceiling facing a target space. The second temperature is an indoor temperature of the target space.

Abstract: In an active region, a first parallel pn layer in which first first-conductivity-type regions and first second-conductivity-type regions are disposed to repeatedly alternate with one another is provided while in a termination region, a second parallel pn layer in which second first-conductivity-type regions and second second-conductivity-type regions are disposed to repeatedly alternate with one another, a first semiconductor region of the second conductivity type and configuring a voltage withstanding structure, and a second semiconductor region of the second conductivity type are provided. An impurity concentration of each of the plurality of first first-conductivity-type regions and the plurality of second first-conductivity-type regions is reduced in proportion to an impurity concentration of a region directly thereabove. The region directly thereabove is the first semiconductor region or the second semiconductor region.

Abstract: A silicon carbide semiconductor device includes a parallel pn layer that includes a standard portion and first and second portions. The standard portion is located at a center of the parallel pn layer in a depth direction and charge balanced. The first and second portions are respectively located closer to the first and second main surfaces than is the standard portion. In the first portion, an amount of a second-conductivity-type charge is greater than that of the first-conductivity-type regions, and continuously increases with a first gradient in a first direction from the standard portion toward the first main surface. In the second portion, an amount of charge of the first-conductivity-type regions is greater than that of the second-conductivity-type regions, and the amount of charge of the second-conductivity-type regions continuously decreases with a second gradient in a second direction from the standard portion toward the second main surface.

Abstract: In an active region, a first parallel pn layer is provided in which a plurality of first first-conductivity-type regions and a plurality of first second-conductivity-type regions are disposed so as to repeatedly alternate with one another; in a termination region, a second parallel pn layer is provided in which a plurality of second first-conductivity-type regions and a plurality of second second-conductivity-type regions are disposed so as to repeatedly alternate one another; in the termination region, a first semiconductor region of a second conductivity type, is selectively provided between a first main surface of a semiconductor substrate and the second parallel pn layer, the first semiconductor region configuring a voltage withstanding structure and surrounding a periphery of the active region. An other second-conductivity-type region between the first semiconductor region and the plurality of second second-conductivity-type regions in a thickness direction is provided and has a thickness of 0.

Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face parallel to a first direction and a second direction perpendicular to the first direction; a first trench, a second trench, and a third trench extending in the first direction; a first region of n-type disposed in the silicon carbide layer; a second region of p-type disposed in the silicon carbide layer, disposed between the first region of n-type and the first face, and disposed between the first trench and the second trench; a sixth region of p-type disposed in the silicon carbide layer and disposed on a bottom surface of the first trench; a seventh region of p-type disposed in the silicon carbide layer and disposed on a bottom surface of the second trench; an eighth region of p-type disposed in the silicon carbide layer and disposed on a bottom surface of the third trench; a ninth region of p-type disposed in the silicon carbide layer and in contact with the sixth region and the second region; and

Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face parallel to a first direction and a second direction crossing the first direction and a second face facing the first face; a first trench on a side of the first face extending in the first direction; a second trench extending in the first direction; a third trench extending in the second direction and continuous with the first trench and the second trench; a fourth trench extending in the first direction, disposed between the first trench and the second trench, and spaced from the third trench in the first direction; a gate electrode in the first to fourth trench; a gate insulating layer; a first conductive layer crossing the third trench and connected to the gate electrode; a first electrode disposed on the first face; and a second electrode disposed on the second face.

Abstract: A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face; a trench in the silicon carbide layer extending in a first direction; a gate electrode disposed in the trench; a first silicon carbide region of n-type; a second silicon carbide region of p-type between the first silicon carbide region and the first face being shallower than the trench; a third silicon carbide region of n-type disposed between the second silicon carbide region and the first face; a fourth silicon carbide region of n-type disposed between the third silicon carbide region and the first face, a width of the fourth silicon carbide region in a second direction perpendicular to the first direction being smaller than a width of the third silicon carbide region in the second direction; and a first electrode in contact with the fourth silicon carbide region.

Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane parallel to a first direction and a second direction orthogonal to the first direction, and a second plane facing the first plane, the silicon carbide layer including a first trench and a second trench extending in the first direction; a gate electrode in the first trench and the second trench; a gate insulating layer; a gate wiring extending in the second direction, intersecting with the first trench and the second trench, connected to the gate electrode; a first electrode; a second electrode; and an interlayer insulating layer provided between the gate electrode and the first electrode. Neither the gate electrode nor the gate wiring is present between an end of the first trench in the first direction and the interlayer insulating layer.

Abstract: A semiconductor device including a semiconductor substrate; a first parallel pn layer in which first first-conductivity-type column regions and first second-conductivity-type column regions repeatedly alternate with one another in an active region; a second parallel pn layer in which second first-conductivity-type column regions and second second-conductivity-type column regions repeatedly alternate with one another, in a termination region; a device structure provided between the first main surface of the semiconductor substrate and the first parallel pn layer; a first electrode provided at the first main surface and electrically connected to the device structure; and a second electrode provided at the second main surface of the semiconductor substrate. The plurality of second first-conductivity-type column regions and the plurality of second second-conductivity-type column regions are disposed in concentric shapes surrounding a perimeter of the first parallel pn layer in a plan view.

Abstract: A semiconductor device including a semiconductor substrate, a parallel pn layer and a device structure provided in the semiconductor substrate, first and second electrodes respectively provided at two main surfaces of the semiconductor substrate, the first electrode being electrically connected to the device structure. The parallel pn layer includes first-conductivity-type column regions and second-conductivity-type column regions that are adjacently disposed and repeatedly alternate with one another in a first direction parallel to the first main surface, that each extend in a second direction parallel to the first main surface and orthogonal to the first direction, and that are of a same impurity concentration. A portion of the second-conductivity-type column regions is shorter than the rest thereof. The parallel pn layer has a first portion and a second portion respectively closer to the first and second main surfaces, the first portion being more p-rich, and less n-rich, than the second portion.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a plurality of trenches, a plurality of gate electrodes respectively provided in the trenches, a first conductive film, a first electrode, a second electrode, a plurality of first high-concentration regions, a plurality of second high-concentration regions, and a second conductive film. The first semiconductor region has a first portion and a plurality of second portions respectively at positions facing the plurality of second high-concentration regions in a depth direction. The second conductive film forms a Schottky contact with the plurality of second portions of the first semiconductor region, such that each junction surface between the second conductive film and the first semiconductor region forms a Schottky barrier of a Schottky barrier diode.

Abstract: A semiconductor device has: a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the first conductivity type; a trench; a gate insulating film; a gate electrode; a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type. The third semiconductor region is provided between the gate insulating film on a sidewall of the trench and the first semiconductor region. The fourth semiconductor region is provided between the first semiconductor region and the third semiconductor region, and has an impurity concentration higher than that of the first semiconductor region.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate having an active region and a termination region that surrounds the active region in a top view, a first parallel pn layer provided in the semiconductor substrate in the active region, a second parallel pn layer provided in the semiconductor substrate in the termination region, a device structure provided in the active region, a first electrode electrically connected to the device structure, a second electrode, a first semiconductor region selectively provided in the termination region, and a second semiconductor region provided between the second parallel pn layer and the first semiconductor region, and in contact with the first semiconductor region. The second parallel pn layer is provided apart from the first semiconductor region, at a position deeper than the first semiconductor region and closer to an end of the semiconductor substrate than an outer end of the first semiconductor region.

Abstract: By a first ion-implantation of a p-type impurity, first and second p+-type regions for mitigating electric field of trench bottoms are formed in surface regions of an n?-type epitaxial layer that constitutes an n?-type drift region. Thereafter, a second ion-implantation of an n-type impurity for reverting a portion of each of the first p+-type regions to the n?-type, and a third ion-implantation of an n-type impurity for an entire surface of the n?-type epitaxial layer, are performed. By the second ion-implantation, first current spreading layer (CSL) portions that constituting n-type current spreading regions are formed facing the first p+-type regions in the depth direction. By the third ion-implantation, the first CSL portions have a predetermined n-type impurity concentration, and second CSL portions constituting the n-type current spreading regions are formed between the first and second p+-type regions and are in contact with the first CSL portions.

Abstract: A semiconductor device having a connecting region between an active region and an edge region. The semiconductor device including a semiconductor substrate, a first semiconductor layer provided on the semiconductor substrate, a second semiconductor layer provided on the first semiconductor layer, a plurality of first semiconductor regions selectively provided in the second semiconductor layer, a plurality of first and second trenches penetrating through the first semiconductor regions and the second semiconductor layer, a plurality of gate electrodes provided in the first trenches, via a plurality of gate insulating films, respectively, and a plurality of Schottky electrodes respectively provided in the second trenches. The semiconductor substrate, the first and second semiconductor layers, the first semiconductor regions, the first trenches, the gate electrodes and the gate insulating films are provided in the active region.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate; a first semiconductor region and a second semiconductor region provided in the semiconductor substrate; a plurality of third semiconductor regions selectively provided in the semiconductor substrate, a plurality of first and second trenches penetrating through the second and third semiconductor regions and reaching the first semiconductor region; a plurality of gate electrodes respectively provided in the first trenches; a plurality of conductive films respectively embedded in the second trenches, junction interfaces between the first semiconductor region and the conductive films forming a plurality of Schottky barriers; a first electrode and a second electrode; and a plurality of Schottky barrier diodes that respectively include the plurality of Schottky barriers.

Abstract: A superjunction semiconductor device having a termination structure portion surrounding an active region in a plan view. The device includes: a semiconductor substrate; a first semiconductor layer provided on the semiconductor substrate; and a parallel pn structure and a channel stopper provided in the first semiconductor layer. The channel stopper surrounds the parallel pn structure in the plan view, and contacts the parallel pn structure in the termination structure portion. The parallel pn structure includes a plurality of first columns each having a first width and a plurality of second columns each having a second width that repeatedly alternate one another parallel to the main surface. In a region of the parallel pn structure contacting the channel stopper, a product of the second width and an impurity concentration of the second columns is less than a product of the first width and an impurity concentration of the first columns.

Abstract: An n--type drift layer is an n--type epitaxial layer doped with nitrogen as an n-type dopant and is co-doped with aluminum as a p-type dopant, the n--type drift layer containing the nitrogen and aluminum substantially uniformly throughout. An n-type impurity concentration of the n--type drift layer is an impurity concentration determined by subtracting the aluminum concentration from the nitrogen concentration of the n--type drift layer; a predetermined blocking voltage is realized by the impurity concentration. A combined impurity concentration of the nitrogen and aluminum of the n--type drift layer is at least 3×1016/cm3.