Patents by Inventor Shinsuke Nakano
Shinsuke Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240328985Abstract: An electrode substrate includes an insulation substrate and a reference electrode on the insulation substrate. The reference electrode includes a silver layer, a first silver chloride layer, and a second silver chloride layer. The silver layer is on the insulation substrate. The first silver chloride layer is on the silver layer on the insulation substrate, and covers the silver layer. The second silver chloride layer is on the first silver chloride layer on the insulation substrate, and covers the first silver chloride layer. An area void fraction of the first silver chloride layer is larger than an area void fraction of the second silver chloride layer in any longitudinal section.Type: ApplicationFiled: May 30, 2024Publication date: October 3, 2024Inventors: Naruto MIYAKAWA, Ayumi SHINAGAWA, Tomomi NAKANO, Shota USHIBA, Shinsuke TANI
-
Patent number: 12066735Abstract: In a terminator, a midpoint electrode is provided between a first signal electrode and a second signal electrode, a first resistor is connected between the first signal electrode and the midpoint electrode, a second resistor is connected between the second signal electrode and the midpoint electrode, a first GND electrode is provided on a side opposite to the side where the first resistor is provided with the first signal electrode interposed therebetween, a second GND electrode is provided on the side opposite to the side where the second resistor is provided with the second signal electrode interposed therebetween, and capacitances in the terminator are formed between the first signal electrode and the midpoint electrode, between the second signal electrode and the midpoint electrode, between the first signal electrode and the first GND electrode, and between the second signal electrode and the second GND electrode.Type: GrantFiled: September 11, 2019Date of Patent: August 20, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Shigeru Kanazawa, Hiromasa Tanobe, Josuke Ozaki, Shinsuke Nakano, Nobuhiro Kikuchi
-
Patent number: 12050484Abstract: A clock generation circuit includes a mode-locked laser that generates an optical pulse, a photodiode that photoelectrically converts the optical pulse generated by the mode-locked laser, and a filter that attenuates at least one of a DC component and a harmonic component of the mode-locked laser included in an electric signal output from the photodiode.Type: GrantFiled: April 17, 2019Date of Patent: July 30, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Kenji Tanaka, Naoki Miura, Shinsuke Nakano, Hideyuki Nosaka
-
Patent number: 11462883Abstract: A CMOS inverter circuit is provided as a circuit to modulate a current flowing into a laser diode on the basis of a digital signal. An amplitude of a current flowing in a PMOSFET in the CMOS inverter circuit is made to contribute to an amplitude of the current flowing into the laser diode, to reduce an input amplitude.Type: GrantFiled: February 22, 2019Date of Patent: October 4, 2022Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Toshiki Kishi, Munehiko Nagatani, Shinsuke Nakano, Hideyuki Nosaka
-
Patent number: 11372307Abstract: Provided is an optical modulator having an optical modulation high frequency line through which a high frequency electrical signal can be efficiently input to an optical modulation region and which is in a broadband. High frequency lines of an optical modulator, that is, an input high frequency line, an optical modulation high frequency line, and an output high frequency line have a line configuration in which each of the input high frequency line and the output high frequency line is divided into a plurality of segments, and adjacent segments of the plurality of the segments have different characteristic impedances and propagation constants. The input high frequency line and the output high frequency line may be implemented by changing a width or a thickness of a signal electrode formed on a dielectric forming a micro-strip line between adjacent segments.Type: GrantFiled: March 6, 2019Date of Patent: June 28, 2022Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Nobuhiro Kikuchi, Eiichi Yamada, Josuke Ozaki, Yoshihiro Ogiso, Yuta Ueda, Shinsuke Nakano
-
Patent number: 11323084Abstract: A linear amplifier includes a pre-amplifier configured to amplify an input differential signal, a post-amplifier configured to amplify an output signal of the pre-amplifier, an amplitude detector configured to detect an amplitude of an output signal of the post-amplifier, and an output voltage corresponding to the detected amplitude, a comparator configured to control a tail current source of the pre-amplifier such that when the output voltage of the amplitude detector is less than or equal to a reference voltage, a tail current of the pre-amplifier is set to a constant value, and when the output voltage of the amplitude detector is larger than the reference voltage, the tail current is reduced to make the output voltage of the amplitude detector equal to the reference voltage.Type: GrantFiled: October 16, 2019Date of Patent: May 3, 2022Assignee: Nippon Telegraph and Telephone CorporationInventors: Teruo Jo, Shinsuke Nakano, Munehiko Nagatani
-
Patent number: 11233393Abstract: A reception-side IC chip (1a) includes a pad (15) which is connected to a transmission line (2) which is outside the chip and has a characteristic impedance Z0 of 50?, a signal line (16), one end of which is connected to the pad (15), a reception-side input unit circuit (10) configured to receive a signal (S) transmitted from a transmission-side IC chip via the transmission line (2), a 50-? termination resistor (11), for impedance matching, which is connected between a predetermined voltage and the other end of the signal line (16) and is configured to terminate the transmission line (2), and a capacitor (12) inserted between a node (A) of the signal line (16) and the termination resistor (11) and an input terminal (In) of the reception-side input unit circuit (10). A DC-blocking circuit is formed by the capacitor (12).Type: GrantFiled: December 13, 2018Date of Patent: January 25, 2022Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Munehiko Nagatani, Hideyuki Nosaka, Shinsuke Nakano
-
Publication number: 20210359655Abstract: A linear amplifier includes a pre-amplifier configured to amplify an input differential signal, a post-amplifier configured to amplify an output signal of the pre-amplifier, an amplitude detector configured to detect an amplitude of an output signal of the post-amplifier, and an output voltage corresponding to the detected amplitude, a comparator configured to control a tail current source of the pre-amplifier such that when the output voltage of the amplitude detector is less than or equal to a reference voltage, a tail current of the pre-amplifier is set to a constant value, and when the output voltage of the amplitude detector is larger than the reference voltage, the tail current is reduced to make the output voltage of the amplitude detector equal to the reference voltage.Type: ApplicationFiled: October 16, 2019Publication date: November 18, 2021Inventors: Teruo Jo, Shinsuke Nakano, Munehiko Nagatani
-
Publication number: 20210341812Abstract: In a terminator, a midpoint electrode is provided between a first signal electrode and a second signal electrode, a first resistor is connected between the first signal electrode and the midpoint electrode, a second resistor is connected between the second signal electrode and the midpoint electrode, a first GND electrode is provided on a side opposite to the side where the first resistor is provided with the first signal electrode interposed therebetween, a second GND electrode is provided on the side opposite to the side where the second resistor is provided with the second signal electrode interposed therebetween, and capacitances in the terminator are formed between the first signal electrode and the midpoint electrode, between the second signal electrode and the midpoint electrode, between the first signal electrode and the first GND electrode, and between the second signal electrode and the second GND electrode.Type: ApplicationFiled: September 11, 2019Publication date: November 4, 2021Inventors: Shigeru Kanazawa, Hiromasa Tanobe, Josuke Ozaki, Shinsuke Nakano, Nobuhiro Kikuchi
-
Publication number: 20210216097Abstract: A clock generation circuit includes a mode-locked laser that generates an optical pulse, a photodiode that photoelectrically converts the optical pulse generated by the mode-locked laser, and a filter that attenuates at least one of a DC component and a harmonic component of the mode-locked laser included in an electric signal output from the photodiode.Type: ApplicationFiled: April 17, 2019Publication date: July 15, 2021Inventors: Kenji Tanaka, Naoki Miura, Shinsuke Nakano, Hideyuki Nosaka
-
Publication number: 20210175706Abstract: A reception-side IC chip (1a) includes a pad (15) which is connected to a transmission line (2) which is outside the chip and has a characteristic impedance Z0 of 50 ?, a signal line (16), one end of which is connected to the pad (15), a reception-side input unit circuit (10) configured to receive a signal (S) transmitted from a transmission-side IC chip via the transmission line (2), a 50-? termination resistor (11), for impedance matching, which is connected between a predetermined voltage and the other end of the signal line (16) and is configured to terminate the transmission line (2), and a capacitor (12) inserted between a node (A) of the signal line (16) and the termination resistor (11) and an input terminal (In) of the reception-side input unit circuit (10). A DC-blocking circuit is formed by the capacitor (12).Type: ApplicationFiled: December 13, 2018Publication date: June 10, 2021Inventors: Munehiko NAGATANI, Hideyuki NOSAKA, Shinsuke NAKANO
-
Publication number: 20210091533Abstract: A CMOS inverter circuit is provided as a circuit to modulate a current flowing into a laser diode on the basis of a digital signal. An amplitude of a current flowing in a PMOSFET in the CMOS inverter circuit is made to contribute to an amplitude of the current flowing into the laser diode, to reduce an input amplitude.Type: ApplicationFiled: February 22, 2019Publication date: March 25, 2021Inventors: Toshiki Kishi, Munehiko Nagatani, Shinsuke Nakano, Hideyuki Nosaka
-
Publication number: 20210080795Abstract: Provided is an optical modulator having an optical modulation high frequency line through which a high frequency electrical signal can be efficiently input to an optical modulation region and which is in a broadband. High frequency lines of an optical modulator, that is, an input high frequency line, an optical modulation high frequency line, and an output high frequency line have a line configuration in which each of the input high frequency line and the output high frequency line is divided into a plurality of segments, and adjacent segments of the plurality of the segments have different characteristic impedances and propagation constants. The input high frequency line and the output high frequency line may be implemented by changing a width or a thickness of a signal electrode formed on a dielectric forming a micro-strip line between adjacent segments.Type: ApplicationFiled: March 6, 2019Publication date: March 18, 2021Inventors: Nobuhiro Kikuchi, Eiichi Yamada, Josuke Ozaki, Yoshihiro Ogiso, Yuta Ueda, Shinsuke Nakano
-
Patent number: 10950293Abstract: A signal processing circuit is provided that generates output signals to be output from spatially different output ports based on bit combinations of an input word consisting of a plurality of bit signals. A distributed memory, a ROM and a DAC in which the signal processing circuit is used are also provided. A recognition circuit includes a serial port to which a bit signal is input and 2N output ports recognizing an input N-bit word and corresponding uniquely to 2N bit combinations. Output ports of the recognition circuit are connected to 2N input ports of an electric circuit. With no signal input to the recognition circuit, all outputs are constantly in a Low level state. In a case where a bit signal is input to the serial port of the recognition circuit, only one of the output ports corresponding to the bit combinations turns to a High level state.Type: GrantFiled: April 19, 2018Date of Patent: March 16, 2021Assignee: Nippon Telegraph and Telephone CorporationInventors: Salaheldin Ahmed Ezzeldin Ibrahim Mohamed, Youhei Sakamaki, Shinsuke Nakano, Kota Shikama, Yuko Kawajiri
-
Patent number: 10892716Abstract: An amplifier applied to TIA is provided to suppress the noise caused by a current source. An amplifier constituting a transimpedance amplifier includes an inductor element inserted between a current source connected to an input terminal of an amplification stage and a power source voltage line. The current source includes a first transistor in which a base terminal is connected to a current control bias and a collector terminal is connected to the input terminal. The inductor element is inserted between the emitter terminal of the first transistor and the power source voltage line.Type: GrantFiled: July 1, 2016Date of Patent: January 12, 2021Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Shinsuke Nakano, Hiroaki Katsurai, Masafumi Nogawa, Shunji Kimura, Masatoshi Tobayashi, Shigehiro Kurita, Masahiro Endo
-
Patent number: 10804857Abstract: An amplifier typically exemplified by a TIA is realized that provides an optimal band characteristic, that reduces the possibility of the oscillation, and that achieves a reduced dispersion of the band characteristics. An amplifier for amplifying an electric signal, comprising: a first buffer for amplifying the electric signal; a filter that is connected to an output of the first buffer and that includes a parallel circuit consisting of an inductor and a first capacity; and a second buffer connected to an output of the filter.Type: GrantFiled: May 15, 2018Date of Patent: October 13, 2020Assignees: NIPPON TELEGRAPH AND TELEPHONE CORPORATION, NTT ELECTRONICS CORPORATIONInventors: Masafumi Nogawa, Shinsuke Nakano, Hiroaki Sanjoh, Masatoshi Tobayashi, Yoshikazu Urabe, Masahiro Endo
-
Patent number: 10666212Abstract: A positive-side power supply terminal (1-1a) of a differential amplifier (1-1) is connected to a positive-side power supply line (L1). A negative-side power supply terminal (1-2b) of a differential amplifier (1-2) is connected to a negative-side power supply line (L2). A negative-side power supply terminal (1-1b) of the differential amplifier (1-1) and a positive-side power supply terminal (1-2a) of the differential amplifier (1-2) are connected to each other. A final-stage amplifier (2) is connected between the positive-side power supply line (L1) and the negative-side power supply line (L2).Type: GrantFiled: March 15, 2017Date of Patent: May 26, 2020Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka
-
Publication number: 20200135256Abstract: A signal processing circuit is provided that generates output signals to be output from spatially different output ports based on bit combinations of an input word consisting of a plurality of bit signals. A distributed memory, a ROM and a DAC in which the signal processing circuit is used are also provided. A recognition circuit includes a serial port to which a bit signal is input and 2N output ports recognizing an input N-bit word and corresponding uniquely to 2N bit combinations. Output ports of the recognition circuit are connected to 2N input ports of an electric circuit. With no signal input to the recognition circuit, all outputs are constantly in a Low level state. In a case where a bit signal is input to the serial port of the recognition circuit, only one of the output ports corresponding to the bit combinations turns to a High level state.Type: ApplicationFiled: April 19, 2018Publication date: April 30, 2020Inventors: Salaheldin Ahmed Ezzeldin Ibrahim Mohamed, Youhei Sakamaki, Shinsuke Nakano, Kota Shikama, Yuko Kawajiri
-
Patent number: 10637207Abstract: A driver circuit 11 includes a plurality of cascode-connected NMOS transistors, a modulating signal VGN1 is applied to a gate terminal of a lowermost stage transistor TN1 located at a lowermost stage out of the NMOS transistors, and an upper stage bias potential VGN2 that is a sum of a minimum gate-source voltage VGN1min and a maximum drain-source voltage VDS1max of a transistor (TN1) located immediately below an upper stage transistor located at an upper stage above the lowermost stage transistor of the NMOS transistors is applied to the upper stage transistor TN2.Type: GrantFiled: October 16, 2017Date of Patent: April 28, 2020Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Toshiki Kishi, Munehiko Nagatani, Shinsuke Nakano, Hiroaki Katsurai, Masafumi Nogawa, Hideyuki Nosaka
-
Publication number: 20200036344Abstract: An amplifier applied to TIA is provided to suppress the noise caused by a current source. An amplifier constituting a transimpedance amplifier includes an inductor element inserted between a current source connected to an input terminal of an amplification stage and a power source voltage line. The current source includes a first transistor in which a base terminal is connected to a current control bias and a collector terminal is connected to the input terminal. The inductor element is inserted between the emitter terminal of the first transistor and the power source voltage line.Type: ApplicationFiled: July 1, 2016Publication date: January 30, 2020Inventors: Shinsuke Nakano, Hiroaki Katsurai, Masafumi Nogawa, Shunji Kimura, Masatoshi Tobayashi, Shigehiro Kurita, Masahiro Endo