Abstract: Memory cells, which serve as basic cells, are arranged in a matrix pattern. The memory cells are each provided with a word line which is integral with the gate electrode of a switch element and which is formed of polysilicon. A metallic interconnection layer is arranged above the word line and is applied with substantially the same potential as the word line. The metallic interconnection layer and the word line are connected together via through-holes. The through-holes are formed in through-hole cells, which also serve as basic cells. The through-hole cells and the memory cells are arranged such that the number of rows of the former and the number of rows of the latter are in the ratio of one to at least two.

Abstract: According to this invention, there is disclosed a semiconductor device in which a memory section and a logic section are arranged on the same semiconductor chip, comprising a high-resistance element constituting a memory cell, a low-resistance line connected to the high-resistance element, a power source line serving as a power source path from a power source pad, a switching element arranged between the low-resistance line and the power source line, and a control circuit for controlling the switching element.

Abstract: The present invention relates to a semiconductor memory cell. The memory cell comprises a word line, a pair of bit lines crossing the word line, a resistance having a first side connected to a high power source and a second side connected to a first connecting node, a first FET connected between the first connecting node and a low power source and having a gate connected to a second connecting node, a second FET connected between the second connecting node and the low power source and having a gate connected to the first connecting node, a third FET connected between the first connecting node and one of the pair of bit lines and having a gate connected to the word line to control the operation of the third FET by changing the potential of the word line, and a fourth FET connected between the second connecting node and the other of the pair of bit lines and having a gate connected to the word line to control the operation of the fourth FET by changing the potential of the word line.

Abstract: A plurality of standard cells are placed on a semiconductor substrate. A first aluminum wiring layer is connected to those standard cells. Below the first aluminum wiring layer, a second wiring layer is formed which is not connected to the standard cells and which, together with the first wiring layer, forms a capacitor. Between the first and second aluminum wiring layers, an insulating layer is formed. Wiring skew is adjusted by making through-holes in the insulating layer, and connecting the first and second aluminum wiring layers to each other via as many through-holes as required to vary the capacitance between them.