Abstract: A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first stepped word line contact region, and a second set of word line contacts in contact with a contact portion of respective even numbered word lines in a second stepped word line contact region. The even numbered word lines in the first word line contact region do not contact a word line contact while the odd numbered word lines in the second word line contact region do not contact a word line contact.

Abstract: A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

Abstract: A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers.

Abstract: A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.

Abstract: A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first stepped word line contact region, and a second set of word line contacts in contact with a contact portion of respective even numbered word lines in a second stepped word line contact region. The even numbered word lines in the first word line contact region do not contact a word line contact while the odd numbered word lines in the second word line contact region do not contact a word line contact.

Abstract: A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.

Abstract: Methods of fabricating semiconductor devices, such as monolithic three-dimensional NAND memory string devices, include selectively forming semiconductor material charge storage regions over first material layers exposed on a sidewall of a front side opening extending through a stack comprising an alternating plurality of first and second material layers using a difference in incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material of the stack. In other embodiments, a silicon layer is selectively deposited on silicon nitride on a surface having at least one first portion including silicon oxide and at least one second portion including silicon nitride using a difference in an incubation time for the silicon on silicon nitride relative to an incubation time for the silicon on silicon oxide.

Abstract: A memory opening is formed through a stack of alternating layers comprising first material layers and second material layers. Sidewall surfaces of the second material layers are laterally recessed with respect to sidewall surfaces of the first material layers within the memory opening. Annular semiconductor material portions can be formed by depositing a semiconductor material from the sidewall surfaces of the second material layers while the semiconductor material does not grow from surfaces of the first material layers. Optionally, an inner portion of each annular semiconductor material portion can be converted into an annular dielectric material portion that includes a dielectric material. A memory film is formed in the memory opening. During removal of the second material layers, the annular semiconductor material portions can be employed as an etch stop material, thereby minimizing collateral etching of the memory film or annular dielectric material portions.

Abstract: A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first stepped word line contact region, and a second set of word line contacts in contact with a contact portion of respective even numbered word lines in a second stepped word line contact region. The even numbered word lines in the first word line contact region do not contact a word line contact while the odd numbered word lines in the second word line contact region do not contact a word line contact.

Abstract: The threshold voltage for vertical transistors in three-dimensional memory stack structures can be made independent of a lateral distance from a source region by forming a doped pocket region. The doped pocket region has the same conductivity type as a doped well that constitutes horizontal portions of the semiconductor channels that extend into the memory stack structures, and has a higher dopant concentration level than the doped well. The doped pocket region and a source region can be simultaneously formed by implanting p-type dopants and n-type dopants into a surface portion of the substrate underlying a backside contact trench. By selecting dopant species having different diffusion rates, the doped pocket region can surround the source region. The process parameters of the anneal process can be selected such that the interface between the dopant pocket region and the doped well underlies outermost memory stack structures.

Abstract: A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers.

Abstract: A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

Abstract: A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.