Abstract: A compound includes: at least one group represented by a formula (11) below; and a single benz[de]anthracene derivative skeleton represented by a formula (1000) below in a molecule, in which Ar1 is a substituted or unsubstituted aryl group including at least four rings, at least one of R10 to R19 is a group represented by the formula (11), L1 is a substituted or unsubstituted arylene group having 6 to 15 ring carbon atoms or a substituted or unsubstituted divalent heterocyclic group having 5 to 15 ring atoms, and mx is 1, 2, or 3.

Abstract: A compound is represented by a formula (1) below. In the formula (1): R1 to R9, R101 to R108, and R111 to R118 are each independently a hydrogen atom, a substituted or unsubstituted aryl group having 6 to 20 ring carbon atoms, or the like; Ar12 is a substituted or unsubstituted aryl group having 10 to 30 ring carbon atoms or the like; p is 0 or 1; q is 0 or 1; and p+q is 1 or 2.

Abstract: A simulation apparatus has: a first processing part configured to obtain a value of a parameter in a first set relating to the forming of the pattern; a second processing part configured to obtain a value of a parameter in a second set that is at least partially same as the parameter in the first set and relating to the forming of the pattern; and an integration processing part configured to evaluate, based on the value of the parameter in the first set and the value of the parameter in the second set, a state of the pattern formed on the substrate and a forming condition when the pattern is formed, and to determine based on the result of the evaluation whether or not to make at least one of the first processing part and the second processing part recalculate the value of the parameter in the corresponding set.

Abstract: A simulation apparatus has: a first processing part configured to obtain a value of a parameter in a first set relating to the forming of the pattern; a second processing part configured to obtain a value of a parameter in a second set that is at least partially same as the parameter in the first set and relating to the forming of the pattern; and an integration processing part configured to evaluate, based on the value of the parameter in the first set and the value of the parameter in the second set, a state of the pattern formed on the substrate and a forming condition when the pattern is formed, and to determine based on the result of the evaluation whether or not to make at least one of the first processing part and the second processing part recalculate the value of the parameter in the corresponding set.

Abstract: A simulation apparatus has: a first processing part configured to obtain a value of a parameter in a first set relating to the forming of the pattern; a second processing part configured to obtain a value of a parameter in a second set that is at least partially same as the parameter in the first set and relating to the forming of the pattern; and an integration processing part configured to evaluate, based on the value of the parameter in the first set and the value of the parameter in the second set, a state of the pattern formed on the substrate and a forming condition when the pattern is formed, and to determine based on the result of the evaluation whether or not to make at least one of the first processing part and the second processing part recalculate the value of the parameter in the corresponding set.

Abstract: Provided is a storage system which is connected to a host computer and whereby data is read and written. The storage system comprises: a storage device which stores the data; and a storage controller wherein an error is detected by one of a plurality of first sections which are sections upon a transfer path of the data with respect to the storage device in a full check mode, an error is detected by one of second sections which are fewer than the first sections in a regular mode, and a switch is made to the full check mode when the error is detected in the regular mode.

Abstract: In a storage system, first and second controllers have respective first and second buffer and cache areas. The first controller stores write data in accordance with a write request in the first cache area without involving the first buffer area and to transfer the stored write data to the second cache area without involving the second buffer area. The first controller is configured to determine which of the first and second cache areas is to be used as a copy source and to be used as a copy destination depending on whether the storing of the first write data in the first cache area had been successful or on whether the transfer of the write data from the first cache area to the second controller had been successful, and by copying data from the copy source to the copy destination, recovers data in an area related to a transfer failure.

Abstract: A simulation apparatus has: a first processing part configured to obtain a value of a parameter in a first set relating to the forming of the pattern; a second processing part configured to obtain a value of a parameter in a second set that is at least partially same as the parameter in the first set and relating to the forming of the pattern; and an integration processing part configured to evaluate, based on the value of the parameter in the first set and the value of the parameter in the second set, a state of the pattern formed on the substrate and a forming condition when the pattern is formed, and to determine based on the result of the evaluation whether or not to make at least one of the first processing part and the second processing part recalculate the value of the parameter in the corresponding set.

Abstract: A receiving controller which receives a read request out of first and second storage controllers transfers the read request to an associated controller which is associated with a read source storage area out of the first and second storage controllers when the receiving controller is not the associated controller. It is however the receiving controller that reads the read-target data from a read source storage device, writes the read-target data to a cache memory of the receiving controller, and transmits the read-target data written in the cache memory of the receiving controller to a host apparatus.

Abstract: A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.

Abstract: A control apparatus, in a storage system, accesses a specific storage area in a shared memory by designating a fixed virtual address, even when a capacity of the shared memory in the storage system changes. A space of a physical address indicating a storage area in a plurality of memories in a self-control-subsystem of two control-subsystems and a space of a physical address indicating a storage area in the plurality of memories in the other-control-subsystem are associated with a space of a virtual address used by each of a processor and an input/output device in the self-control-subsystem. Upon receiving data transferred from the other-control-subsystem to the self-control-subsystem, a relay device translates a virtual address indicating a transfer destination of the data designated by the other-control-subsystem into a virtual address in the self-control-subsystem based on an offset determined in advance, and transfers the data to the translated virtual address.

Abstract: The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.

Abstract: The invention provides a technique for improving processing performance of I/O commands in a storage system in which ownership of each LU is introduced. The storage system includes: a disk device having storage regions that are managed as a plurality of logical units; a plurality of processors that process read commands to the disk device; and a cache that the processors can use to process the read commands. An owner processor that is in charge of processing to each logical unit is allocated to each logical unit. When decision is made that dirty data is not present in the cache in a target region of the read command, there are a case where the owner processor of a logical unit that includes the target region processes the read command, and a case where a non-owner processor, as the processor other than the owner processor, processes the read command.

Abstract: Provided is a storage system which is connected to a host computer and whereby data is read and written. The storage system comprises: a storage device which stores the data; and a storage controller wherein an error is detected by one of a plurality of first sections which are sections upon a transfer path of the data with respect to the storage device in a full check mode, an error is detected by one of second sections which are fewer than the first sections in a regular mode, and a switch is made to the full check mode when the error is detected in the regular mode.

Abstract: A receiving controller which receives a read request out of first and second storage controllers transfers the read request to an associated controller which is associated with a read source storage area out of the first and second storage controllers when the receiving controller is not the associated controller. It is however the receiving controller that reads the read-target data from a read source storage device, writes the read-target data to a cache memory of the receiving controller, and transmits the read-target data written in the cache memory of the receiving controller to a host apparatus.

Abstract: In a storage system, first and second controllers have respective first and second buffer and cache areas. The first controller stores write data in accordance with a write request in the first cache area without involving the first buffer area and to transfer the stored write data to the second cache area without involving the second buffer area. The first controller is configured to determine which of the first and second cache areas is to be used as a copy source and to be used as a copy destination depending on whether the storing of the first write data in the first cache area had been successful or on whether the transfer of the write data from the first cache area to the second controller had been successful, and by copying data from the copy source to the copy destination, recovers data in an area related to a transfer failure.

Abstract: A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.

Abstract: A specific object is designated from a captured image captured by an imaging unit of an image processing device. An extraction processing unit extracts the specific object and the coordinates thereof. A composition image generation unit makes segmentation composition points coincide with the coordinates of the specific object at a first trimming ratio with respect to the captured image to thereby generate composition images which are trimming regions. When a calculation unit determines that protrusion regions are present in the composition images, the composition image generation unit generates reduced composition images including the specific object at a second trimming ratio which is lower than the first trimming ratio.

Abstract: The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.

Abstract: According to a storage system of a prior art adopting a cluster structure, various types of large-capacity memories were arranged to enhance the access performance, so that the system required a dedicated control circuit, and there was difficulty in realizing cost reduction and improvement of access performance simultaneously. In order to solve the problems, the present invention provides a storage system in which a group of memories is integrated to MPU memories directly coupled to MPUs in respective controller units, wherein each MPU memory is divided into a duplication information area and a non-duplication information area, and attribute information for controlling accesses thereto are provided.