Patents by Inventor Shinya Konishi

Shinya Konishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240158739
    Abstract: The purpose of the present invention is to provide: an adhesion improver which contains an edible plant-derived component and is used in an edible base material for culturing cells; a cell culturing scaffolding material containing said adhesion improver; and a tissue body containing said cell culturing scaffolding material. A cell culturing scaffolding material suitable for producing cultured meat can be produced by applying an adhesion improver containing an edible plant-derived component to an edible base material for culturing cells.
    Type: Application
    Filed: March 31, 2022
    Publication date: May 16, 2024
    Inventors: Yuka SEKIGUCHI, Tomoko SUDO, Tomoaki HISHIKI, Takahisa KONISHI, Shinya HASHIGUCHI
  • Patent number: 11821795
    Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: November 21, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Yoshio Takazawa, Fumio Tsuchiya, Daisuke Oshida, Naoya Ota, Masaki Shimada, Shinya Konishi
  • Patent number: 11125628
    Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Shinya Konishi, Fumio Tsuchiya, Masaki Shimada
  • Patent number: 11068330
    Abstract: The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Ota, Kan Takeuchi, Fumio Tsuchiya, Masaki Shimada, Shinya Konishi, Daisuke Oshida
  • Publication number: 20210080330
    Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 18, 2021
    Inventors: Kan TAKEUCHI, Yoshio TAKAZAWA, Fumio TSUCHIYA, Daisuke OSHIDA, Naoya OTA, Masaki SHIMADA, Shinya KONISHI
  • Publication number: 20200081757
    Abstract: The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.
    Type: Application
    Filed: August 16, 2019
    Publication date: March 12, 2020
    Inventors: Naoya OTA, Kan TAKEUCHI, Fumio TSUCHIYA, Masaki SHIMADA, Shinya KONISHI, Daisuke OSHIDA
  • Publication number: 20190154518
    Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.
    Type: Application
    Filed: September 10, 2018
    Publication date: May 23, 2019
    Inventors: Kan TAKEUCHI, Shinya KONISHI, Fumio TSUCHIYA, Masaki SHIMADA
  • Publication number: 20180156859
    Abstract: To provide a semiconductor device that can predict wear-out failure with high accuracy based on an accumulated value of degradation stress, such as a power-source voltage or an environmental temperature, imposed to the semiconductor device, the semiconductor device includes a first circuit that holds a first accumulated degradation stress count value, a second circuit that holds a second accumulated degradation stress count value, a third circuit that holds a count value of an accumulated operating time or a value corresponding thereto, and a fourth circuit or an operating unit that receives the first accumulated degradation stress count value, the second accumulated degradation stress count value, and the count value of the accumulated operating time or the value corresponding to the value of the accumulated operating time.
    Type: Application
    Filed: October 27, 2017
    Publication date: June 7, 2018
    Inventors: Kan Takeuchi, Fumio Tsuchiya, Shinya Konishi
  • Publication number: 20180009714
    Abstract: A method of producing a dielectric material by preparing a slurry by mixing a dielectric powder, water, one of an organic-acid metal salt and an inorganic metal salt, and an organic silicon compound, causing the slurry to come into contact with an anion exchange resin to remove an anion derived from the one of the organic-acid metal salt and the inorganic metal salt from the slurry, and drying the slurry to obtain the dielectric material.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Inventors: Kazuhiko Higashide, Shinya Konishi, Shuya Nakao
  • Patent number: 9796631
    Abstract: A method of manufacturing barium titanate powder by dispersing, in a solvent such as ethanol, barium titanate. Then, the barium titanate is separated from the slurry by evaporating the solvent while pressurizing the slurry in a pressure container. Then, the separated barium titanate is subjected to a heat treatment, thereby producing the barium titanate powder.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 24, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinya Konishi, Kazuya Fujii, Kazushige Nada
  • Patent number: 9745204
    Abstract: A method of producing barium titanate that includes making a slurry by dispersing barium titanate powder in a solvent such as ethanol. Then, in a high-pressure vessel, substituting supercritical fluid including carbon dioxide gas, for example, for the solvent in the slurry. Then, separating the barium titanate powder from the supercritical fluid by gasifying the supercritical fluid. Then, performing a heat treatment on the separated barium titanate powders to produce the barium titanate.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: August 29, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinya Konishi, Kazuya Fujii, Junichi Saito
  • Publication number: 20160060175
    Abstract: A method of manufacturing barium titanate powder by dispersing, in a solvent such as ethanol, barium titanate. Then, the barium titanate is separated from the slurry by evaporating the solvent while pressurizing the slurry in a pressure container. Then, the separated barium titanate is subjected to a heat treatment, thereby producing the barium titanate powder.
    Type: Application
    Filed: November 11, 2015
    Publication date: March 3, 2016
    Inventors: Shinya Konishi, Kazuya Fujii, Kazushige Nada
  • Publication number: 20160052794
    Abstract: A method of producing barium titanate that includes making a slurry by dispersing barium titanate powder in a solvent such as ethanol. Then, in a high-pressure vessel, substituting supercritical fluid including carbon dioxide gas, for example, for the solvent in the slurry. Then, separating the barium titanate powder from the supercritical fluid by gasifying the supercritical fluid. Then, performing a heat treatment on the separated barium titanate powders to produce the barium titanate.
    Type: Application
    Filed: November 2, 2015
    Publication date: February 25, 2016
    Inventors: Shinya Konishi, Kazuya Fujii, Junichi Saito
  • Patent number: 8406362
    Abstract: A communication device includes a current information storage unit 130 that stores the bit boundary signal at each of timings at which a sampling clock is updated, a past information storage unit 140 that takes in and stores a signal stored in the current information storage unit 130 when a variation point of a reception signal is detected, and does not update a signal stored therein when no variation point of the reception signal is detected, and a clock selection unit 44 that selects CLKSEL2 used for the sampling of the reception signal from N-phase clocks based on a signal stored in the current information storage unit 130 when a variation point of the reception signal is detected, and selects CLKSEL3 based on a signal stored in the past information storage unit 140 when no variation point of the reception signal is detected.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: March 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Konishi, Norio Arai, Osamu Ohnishi
  • Patent number: 8259886
    Abstract: A communication apparatus including a clock generation circuit outputting a plurality of clocks, each clock having a different phase from the other, a synchronization detection block receiving a sync word and a payload having a predetermined length after receiving the payload, sampling the sync word by using each of the plurality of clocks and to output a first signal indicating a clock or clocks capable of sampling the sync word successfully, the synchronization detection block being capable of sampling the payload by using a clock or clocks, a clock phase selection block coupled to the synchronization detection block to receive the first signal, and a clock gate unit to receive each of the plurality of clocks and the second signal to output the selected one of the plurality of clocks, and not to output a rest of the plurality of the clocks based on the second signal.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: September 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Konishi, Norio Arai
  • Patent number: 8175206
    Abstract: There is provided a communication apparatus capable of reducing power consumption. The communication apparatus in accordance with the present invention includes a synchronization detection block 30 which detects synchronization by performing a receiving process using a plurality of clocks whose phase differs from each other with respect to synchronization information contained in a first frame as well as identifies the synchronization detected clocks as candidate clocks to be selected; a clock phase selection block 40 which selects a sampling clock to be used for sampling of the transmission signal from the candidate clocks to be selected, selects a stop clock separated by a predetermined phase from the selected sampling clock, and outputs an instruction for the stop clock; and a clock gate unit 60 which, terminates supplying the stop clock from the plurality of clocks to the synchronization detection block 30 as well as supplies other clocks to the synchronization detection block 30.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: May 8, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Konishi, Norio Arai
  • Patent number: 8054927
    Abstract: The present invention includes: a synchronous-word detecting unit receives a baseband received signal including a synchronous word and data for each frame, and detects whether or not the synchronous word is coincided with an expected value in the baseband received signal by using an N-(N is an integer of 2 or larger) phase sampling clock; a phase information retaining unit retains phase information accumulatively including results detected for a plurality of frames by the synchronous-word detecting unit, and determines a phase to be sampled on the basis of the retained phase information; a phase selecting unit selects and determines a phase of the sampling clock on the basis of determination by the phase information retaining unit; and a FIFO buffer samples the data from the baseband received signal, and outputs the sampled data.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: November 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Konishi
  • Publication number: 20110007857
    Abstract: A communication device includes a current information storage unit 130 that stores the bit boundary signal at each of timings at which a sampling clock is updated, a past information storage unit 140 that takes in and stores a signal stored in the current information storage unit 130 when a variation point of a reception signal is detected, and does not update a signal stored therein when no variation point of the reception signal is detected, and a clock selection unit 44 that selects CLKSEL2 used for the sampling of the reception signal from N-phase clocks based on a signal stored in the current information storage unit 130 when a variation point of the reception signal is detected, and selects CLKSEL3 based on a signal stored in the past information storage unit 140 when no variation point of the reception signal is detected.
    Type: Application
    Filed: June 4, 2010
    Publication date: January 13, 2011
    Applicant: NEC Electronics Corporation
    Inventors: Shinya Konishi, Norio Arai, Osamu Ohnishi
  • Publication number: 20100150255
    Abstract: A semiconductor integrated circuit includes an oscillation circuit for generating multiple clocks of mutually different phases, and is also characterized in selecting a single clock FCLK_P from among multiple clocks FCLK_P [n-1:0] for use in transmitting IQ Serial transmission signals and, utilizing the FCLK_P to transmit an IQ Serial transmission signal.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 17, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Shinya Konishi, Norio Arai
  • Publication number: 20090323878
    Abstract: A communication apparatus which includes a clock generation circuit outputting a plurality of clocks, each of said plurality of clocks having a different phase from each other; a synchronization detection block receiving a sync word and a payload having a predetermined length after receiving said payload, sampling said sync word by using each of said plurality of clocks and to output a first signal indicating a clock or clocks capable of sampling said sync word successfully, said synchronization detection block being capable of sampling said payload by using a clock or clocks inputted thereinto; a clock phase selection block coupled to said synchronization detection block to-receive said first signal to select one of said plurality of clocks in accordance with said first signal and to output a second signal indicating a selected clock; and a clock gate unit coupled between said clock generation circuit and said synchronization detection block and coupled to said clock phase selection block to receive each of
    Type: Application
    Filed: June 5, 2009
    Publication date: December 31, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Shinya Konishi, Norio Arai