Patents by Inventor Shinya Morita

Shinya Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9463884
    Abstract: Provided are a space debris removing device and a method which enable easy installation of a deceleration device to space debris undergoing a tumbling motion. The space debris removing device includes: a propulsion device (3) for performing approach and attitude control on target debris (1); a capture device (4) having a harpoon (41) which can be ejected toward the target debris (1); an observation device (5) for calculating a capture position (E) and a capture attitude at which the harpoon (41) can be driven into a tank (11) (hollow portion) of the target debris (1) by observing a motion of the target debris (1); a deceleration device (6) directly or indirectly connected to the harpoon (41), for decelerating the target debris (1); and a body part (21) on which the propulsion device (3), the capture device (4), the observation device (5), and the deceleration device (6) are mounted.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 11, 2016
    Assignee: IHI Corporation
    Inventors: Yukihito Kitazawa, Aritsune Kawabe, Kozue Hashimoto, Mitsuharu Sonehara, Masaru Uji, Shinya Morita, Katsuaki Nomura, Ayumi Nakanishi
  • Patent number: 9449990
    Abstract: Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a channel layer, an etch stopper layer to protect a surface of the oxide semiconductor layer, a source-drain electrode, and a gate insulator layer arranged between the gate electrode and the channel layer. The metal elements constituting the oxide semiconductor layer comprise In, Zn and Sn. The hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is controlled to 4 atomic % or lower.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: September 20, 2016
    Assignees: KOBE STEEL, LTD., Samsung Display Co., Ltd.
    Inventors: Aya Miki, Shinya Morita, Hiroshi Goto, Hiroaki Tao, Toshihiro Kugimiya, Byung Du Ahn, Gun Hee Kim, Jin Hyun Park, Yeon Hong Kim
  • Publication number: 20160254622
    Abstract: A signal transmission cable has a cable including a dielectric layer and a metallic layer. The signal transmission cable further includes a connector having a chip with a terminal. The connector includes a substrate having an organic layer, and a portion of the organic layer extends from the substrate so as to form the dielectric layer of the cable. The metallic layer is located on the dielectric layer and is directly connected to the terminal.
    Type: Application
    Filed: May 11, 2016
    Publication date: September 1, 2016
    Inventors: Akira AKIBA, Mitsuo HASHIMOTO, Shinya MORITA, Shun MITARAI, Mikihiro TAKETOMO, Kazunao ONIKI, Koichi IKEDA
  • Patent number: 9362683
    Abstract: A signal transmission cable has a cable including a dielectric layer and a metallic layer. The signal transmission cable further includes a connector having a chip with a terminal. The connector includes a substrate having an organic layer, and a portion of the organic layer extends from the substrate so as to form the dielectric layer of the cable. The metallic layer is located on the dielectric layer and is directly connected to the terminal.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: June 7, 2016
    Assignee: SONY CORPORATION
    Inventors: Akira Akiba, Mitsuo Hashimoto, Shinya Morita, Shun Mitarai, Mikihiro Taketomo, Kazunao Oniki, Koichi Ikeda
  • Patent number: 9362313
    Abstract: Provided is an oxide-semiconductor-based thin film transistor having satisfactory switching characteristics and stress resistance. Change in threshold voltage through stress application is suppressed in the thin film transistor. The thin film transistor of excellent stability comprises a substrate and, formed thereon, at least a gate electrode, a gate insulating film, oxide semiconductor layers, a source-drain electrode, and a passivation film for protecting the gate insulating film, and oxide semiconductor layers, wherein the oxide semiconductor layers are laminated layers comprising a second oxide semiconductor layer consisting of In, Zn, Sn, and O and a first oxide semiconductor layer consisting of In, Ga, Zn, and O. The second oxide semiconductor layer is formed on the gate insulating film. The first oxide semiconductor layer is interposed between the second oxide semiconductor layer and the passivation film.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: June 7, 2016
    Assignee: Kobe Steel, Ltd.
    Inventors: Shinya Morita, Aya Miki, Hiroaki Tao, Toshihiro Kugimiya
  • Patent number: 9343586
    Abstract: Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 5% or more; In: 25% or less (excluding 0%); Zn: 35 to 65%; and Sn: 8 to 30%.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: May 17, 2016
    Assignee: Kobe Steel, Ltd.
    Inventors: Hiroshi Goto, Aya Miki, Tomoya Kishi, Kenta Hirose, Shinya Morita, Toshihiro Kugimiya
  • Patent number: 9324882
    Abstract: A thin film transistor containing at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate containing a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 8% or more and 30% or less; In: 25% or less, excluding 0%; Zn: 35% or more to 65% or less; and Sn: 5% or more to 30% or less.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: April 26, 2016
    Assignees: Kobe Steel, Ltd., Samsung Display Co., Ltd.
    Inventors: Hiroshi Goto, Aya Miki, Tomoya Kishi, Kenta Hirose, Shinya Morita, Toshihiro Kugimiya, Byung Du Ahn, Gun Hee Kim, Yeon Hong Kim
  • Patent number: 9318507
    Abstract: Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; two or more oxide semiconductor layers that are used as a channel layer; an etch stopper layer for protecting the surfaces of the oxide semiconductor layers; a source-drain electrode; and a gate insulator film interposed between the gate electrode and the channel layer. The metal elements constituting an oxide semiconductor layer that is in direct contact with the gate insulator film are In, Zn and Sn. The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 19, 2016
    Assignee: Kobe Steel, Ltd.
    Inventors: Aya Miki, Shinya Morita, Hiroshi Goto, Hiroaki Tao, Toshihiro Kugimiya
  • Publication number: 20160099357
    Abstract: Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 5% or more; In: 25% or less (excluding 0%); Zn: 35 to 65%; and Sn: 8 to 30%.
    Type: Application
    Filed: May 26, 2015
    Publication date: April 7, 2016
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.)
    Inventors: Hiroshi GOTO, Aya MIKI, Tomoya KISHI, Kenta HIROSE, Shinya MORITA, Toshihiro KUGIMIYA
  • Patent number: 9299474
    Abstract: There is provided an oxide for semiconductor layers of thin-film transistors, which oxide can provide thin-film transistors with excellent switching characteristics and by which oxide favorable characteristics can stably be obtained even after the formation of passivation layers. The oxide to be used for semiconductor layers of thin-film transistors according to the present invention includes Zn, Sn, and Si.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: March 29, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Shinya Morita, Aya Miki, Yumi Iwanari, Toshihiro Kugimiya, Satoshi Yasuno, Jae Woo Park, Je Hun Lee, Byung Du Ahn
  • Publication number: 20160079437
    Abstract: This thin film transistor comprises, on a substrate, at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and two or more protective films. The oxide semiconductor layer comprises Sn, O and one or more elements selected from the group consisting of In, Ga and Zn. In addition, the two or more protective films are composed of at least a first protective film that is in contact with the oxide semiconductor film, and one or more second protective films other than the first protective film. The first protective film is a SiOx film having a hydrogen concentration of 3.5 atomic % or lower.
    Type: Application
    Filed: June 24, 2014
    Publication date: March 17, 2016
    Applicant: KABUSHIKI KAISHA KOBE SHO (KOBE STEEL, LTD.)
    Inventors: Mototaka OCHI, Shinya MORITA, Yasuyuki TAKANASHI, Hiroshi GOTO, Toshihiro KUGIMIYA
  • Patent number: 9202926
    Abstract: Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IGZO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; In: 25% or less (excluding 0%); Ga: 5% or more; Zn: 30.0 to 60.0%; and Sn: 8 to 30%.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: December 1, 2015
    Assignee: Kobe Steel, Ltd.
    Inventors: Tomoya Kishi, Kenta Hirose, Shinya Morita, Toshihiro Kugimiya
  • Patent number: 9190523
    Abstract: An oxide semiconductor includes a first material including at least one selected from the group consisting of zinc (Zn) and tin (Sn), and a second material, where a value acquired by subtracting an electronegativity difference value between the second material and oxygen (O) from the electronegativity difference value between the first material and oxygen (O) is less than about 1.3.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: November 17, 2015
    Assignees: SAMSUNG DISPLAY CO., LTD., KOBE STEEL, LTD.
    Inventors: Byung Du Ahn, Je Hun Lee, Sei-Yong Park, Jun Hyun Park, Gun Hee Kim, Ji Hun Lim, Jae Woo Park, Jin Seong Park, Toshihiro Kugimiya, Aya Miki, Shinya Morita, Tomoya Kishi, Hiroaki Tao
  • Patent number: 9184298
    Abstract: The interconnect structure of the present invention includes at least a gate insulator layer and an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer is a layered product having a first oxide semiconductor layer containing at least one element (Z group element) selected from the group consisting of In, Ga, Zn and Sn; and a second oxide semiconductor layer containing at least one element (X group element) selected from the group consisting of In, Ga, Zn and Sn and at least one element (Y group element) selected from the group consisting of Al, Si, Ti, Hf, Ta, Ge, W and Ni, and wherein the second oxide semiconductor layer is interposed between the first oxide semiconductor layer and the gate insulator layer.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: November 10, 2015
    Assignee: Kobe Steel, Ltd.
    Inventors: Shinya Morita, Aya Miki, Satoshi Yasuno, Toshihiro Kugimiya
  • Publication number: 20150318400
    Abstract: Provided is a back-channel etch (BCE) thin-film transistor (TFT) without an etch stopper layer, wherein an oxide semiconductor layer of the TFT has excellent resistance to an acid etchant used when forming a source-drain electrode, and has excellent stress stability. The TFT comprises a gate electrode, a gate insulator film, an oxide semiconductor layer, a source-drain electrode, and a passivation film which protects the source-drain electrode, on a substrate. The oxide semiconductor layer comprises one or more elements selected from a group consisting tin, indium, gallium and zinc; and oxygen; and a value in a cross-section in the lamination direction of the TFT, as determined by [100×(the thickness of the oxide semiconductor layer directly below a source-drain electrode end?the thickness in the center portion of the semiconductor layer)/the thickness of the semiconductor layer directly below the source-drain electrode end], is not more than 5%.
    Type: Application
    Filed: December 26, 2013
    Publication date: November 5, 2015
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Shinya MORITA, Mototaka OCHI, Hiroshi GOTO, Toshihiro KUGIMIYA, Kenta HIROSE, Hiroaki TAO, Yasuyuki TAKANASHI
  • Patent number: 9178073
    Abstract: This oxide for a semiconductor layer of a thin-film transistor contains Zn, Sn and In, and the content (at %) of the metal elements contained in the oxide satisfies formulas (1) to (3) when denoted as [Zn], [Sn] and [In], respectively. [In]/([In]+[Zn]+[Sn])??0.53×[Zn]/([Zn]+[Sn])+0.36 (1) [In]/([In]+[Zn]+[Sn])?2.28×[Zn]/([Zn]+[Sn])?2.01 (2) [In]/([In]+[Zn]+[Sn])?1.1×[Zn]/([Zn]+[Sn])?0.32 (3) The present invention enables a thin-film transistor oxide that achieves high mobility and has excellent stress resistance (negligible threshold voltage shift before and after applying stress) to be provided.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: November 3, 2015
    Assignees: Kobe Steel, Ltd., Samsung Display Co., Ltd.
    Inventors: Aya Miki, Shinya Morita, Toshihiro Kugimiya, Satoshi Yasuno, Jae Woo Park, Je Hun Lee, Byung Du Ahn, Gun Hee Kim
  • Publication number: 20150295058
    Abstract: Provided is a back-channel etch type thin-film transistor (TFT) without an etch stopper layer, wherein an oxide semiconductor of the TFT has excellent resistance to an acid etchant and stress stability. The oxide semiconductor layer is a laminate having a first layer comprising tin, indium, and gallium or zinc, and oxygen, and a second layer comprising one or more elements selected from a group consisting indium, zinc, tin and gallium; and oxygen. The TFT is formed, in the following order, a gate insulator film, the second semiconductor layer and the first semiconductor layer; and having a value in a cross section in the lamination direction of the TFT, as determined by [100×(the first layer thickness of directly below a source-drain electrode end?a center portion thickness of the first layer)/the first layer thickness of directly below the source-drain electrode end], of not more than 5%.
    Type: Application
    Filed: December 27, 2013
    Publication date: October 15, 2015
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.)
    Inventors: Shinya Morita, Mototaka Ochi, Hiroshi Goto, Toshihiro Kugimiya, Kenta Hirose
  • Patent number: D771543
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: November 15, 2016
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Shinya Morita, Masahiro Miyake, Masato Terasaki, Naoki Matsumoto, Naonori Akae
  • Patent number: D771772
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: November 15, 2016
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Shinya Morita, Masahiro Miyake, Masato Terasaki, Naoki Matsumoto, Naonori Akae
  • Patent number: D773609
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: December 6, 2016
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Shinya Morita, Masahiro Miyake, Masato Terasaki, Naoki Matsumoto, Naonori Akae