Abstract: According to one embodiment, an anomaly detection apparatus includes a processing circuit. The processing circuit is configured to: acquire measured values from sensors installed in a system, a first function, a first threshold, and a second function to output a second threshold; generate the predicted values based on the measured value and the first function; detect that a deviation between the measured values and the predicted values exceeds the first threshold; calculate the feature quantities based on the measured values; and determine whether a number of consecutive times is equal to or larger than the second threshold to detect an anomaly or a sign of the anomaly.

Abstract: An armature portion includes a first and second armature core, and a core coupling portion that magnetically couples the first armature core to the second armature core. The first and second armature core includes magnetic pole groups that are magnetically coupled, respectively. A first and second magnetic flux are formed in the armature portion by magnets. A first magnetic circuit in which the first magnetic flux flows includes three magnetic pole groups, magnetic field cores, and the magnets. A second magnetic circuit in which the second magnetic flux flows includes two magnetic pole groups, a core coupling structure, the magnetic field cores, and the magnets. This structure reduces magnetic saturation of the magnetic circuit formed on the armature portion and eliminate the need to magnetically divide the armature cores in the machine moving direction, thereby increasing the intensity of the armature.

Abstract: A semiconductor memory device includes a memory cell array and a peripheral circuit. The peripheral circuit includes a plurality of first nodes disposed corresponding to a plurality of first via electrodes, a charging circuit that charges the plurality of first nodes, a discharging circuit that discharges the plurality of first nodes, an address select circuit that electrically conducts one of the plurality of first nodes with the charging circuit or the discharging circuit in response to an input address signal, a plurality of first transistors each disposed in a current path between two of the plurality of first nodes, and a plurality of amplifier circuits that are disposed corresponding to the plurality of first via electrodes and include input terminals connected to any of the plurality of first nodes and output terminals connected to any of the plurality of first via electrodes.

Abstract: A suspension body for an elevator includes a core having a belt-like shape, and a covering layer. The core includes a load bearing layer. The load bearing layer is formed of an impregnation resin and a plurality of high-strength fibers. The covering layer covers at least a part of an outer periphery of the core. The plurality of high-strength fibers include a plurality of kinds of high-strength fibers.

Abstract: A semiconductor device includes first and second gate electrodes, a semiconductor layer between the first and second gate electrodes and extending along a first direction, a first gate insulating layer between the first gate electrode and the semiconductor layer, a second gate insulating layer between the second gate electrode and the semiconductor layer, a first insulating layer including a first region adjacent to the first gate electrode in the first direction and contacting the semiconductor layer, and a second insulating layer extending including a second region adjacent to the second gate electrode in the first direction and contacting the semiconductor layer. An interface between the first region and the semiconductor layer in a direction crossing the first direction is adjacent to the first gate electrode in the first direction.

Abstract: A semiconductor memory device includes a first semiconductor layer, first conductive layers, electric charge accumulating portions, a first conductivity-typed second semiconductor layer, a first wiring, a second conductivity-typed third semiconductor layer, and a second conductive layer. The first semiconductor layer extends in a first direction. First conductive layers are arranged in the first direction and extend in a second direction. Electric charge accumulating portions are disposed between the first semiconductor layer and first conductive layers. The second semiconductor layer is connected to one end of the first semiconductor layer. The first wiring is connected to the first semiconductor layer via the second semiconductor layer. The third semiconductor layer is connected to a side surface in a third direction of the first semiconductor layer. The second conductive layer extends in the second direction and is connected to the first semiconductor layer via the third semiconductor layer.

Abstract: An electric machine that increases structural freedom to increase output of the electric machine while satisfying requirements of an outer shape. An armature portion includes armature cores (H1, H2) and a plurality of coils (CL) attached to the armature core (H1). A magnetic field portion (Fs) is relatively rotatable to the armature portion and includes a plurality of magnets (Mg) and a plurality of magnetic field cores (22N, 22S). In the magnetic field portion (Fs), the magnets (Mg) are disposed between two magnetic field cores (22N, 22S) adjacent in a rotation direction. Each of the armature cores (H1, H2) includes magnetic pole groups (G1, G2). The magnetic pole group (G1) included in the armature core (H1) and the magnetic pole group (G2) included in the armature core (H2) constitute a magnetic pole group pair (P) that forms a magnetic path through the magnetic field portion (Fs).

Abstract: A suspension body for an elevator includes a core having a belt-like shape, and a covering layer covering at least a part of an outer periphery of the core. The core includes a load bearing layer. The load bearing layer is formed of an impregnation resin and a plurality of high-strength fibers. Further, the load bearing layer is divided into a plurality of segment layers arranged apart from each other in a thickness direction of the core. An intermediate layer made of a material different from that for the load bearing layer is interposed between the segment layers adjacent to each other in the thickness direction of the core.

Abstract: A semiconductor device includes first and second gate electrodes, a semiconductor layer between the first and second gate electrodes and extending along a first direction, a first gate insulating layer between the first gate electrode and the semiconductor layer, a second gate insulating layer between the second gate electrode and the semiconductor layer, a first insulating layer including a first region adjacent to the first gate electrode in the first direction and contacting the semiconductor layer, and a second insulating layer extending including a second region adjacent to the second gate electrode in the first direction and contacting the semiconductor layer. An interface between the first region and the semiconductor layer in a direction crossing the first direction is adjacent to the first gate electrode in the first direction.

Abstract: A suspension body for an elevator includes a core having a belt-like shape, and a covering layer. The core includes a load bearing layer. The load bearing layer is formed of an impregnation resin and a plurality of high-strength fibers. The covering layer covers at least a part of an outer periphery of the core. The plurality of high-strength fibers include a plurality of kinds of high-strength fibers.

Abstract: A dynamic balancing test and correction apparatus capable of shortening the time required for correcting imbalance in a correction part and improving the entire workflow of the apparatus.

Abstract: According to an embodiment, a semiconductor device has a first and second region, and a semiconductor channel. The first region includes a peak of a concentration profile of a first impurity of a first conductivity type. The first region extends from a surface of the substrate, through a depth range including the concentration profile of a second impurity of a second conductivity type, to a depth of an intersection of the concentration profile of the first impurity and the concentration profile of the second impurity. The second region includes a concentration profile of a third impurity, and the second region overlaps at least part of the first region. The concentration profile of the third impurity is higher in concentration than the concentration profile of the first impurity throughout a depth direction of the second region. One end of the semiconductor channel reaches the first and second region.

Abstract: An electronic device housing of the present invention is a housing for internally accommodating an electronic device and is provided with a metal bottom plate, and metal side plates folded and integrally connected to the bottom plate, in which, in a metal member (M) formed of at least the bottom plate and the side plate, a thermoplastic resin member is joined to a portion of the surface of the plate-shaped metal member (M), the metal member (M) is reinforced by a thermoplastic resin member, and the thermoplastic resin member is joined to both surfaces of the plate-shaped metal member (M).

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, and a first pillar. The first conductive layer is provided above the substrate and includes a first N-type semiconductor region and a first P-type semiconductor region. The second conductive layers are provided above the first conductive layer and stacked at intervals. The first pillar includes a first semiconductor layer and a first insulating layer. The first semiconductor layer is provided through the second conductive layers and is in contact with each of the first N-type semiconductor region and the first P-type semiconductor region. The first insulating layer is provided between the first semiconductor layer and the second conductive layers.

Abstract: A suspension body for an elevator includes a core having a belt-like shape, and a covering layer covering at least a part of an outer periphery of the core. The core includes a load bearing layer. The load bearing layer is formed of an impregnation resin and a plurality of high-strength fibers. Further, the load bearing layer is divided into a plurality of segment layers arranged apart from each other in a thickness direction of the core. An intermediate layer made of a material different from that for the load bearing layer is interposed between the segment layers adjacent to each other in the thickness direction of the core.

Abstract: According to one embodiment, there is provided a semiconductor device including a first semiconductor region, a stacked body, a semiconductor channel, a gate insulating film, and a control circuit. The stacked body is of conductive films arranged in a stacking direction with an insulator interposed. The semiconductor channel penetrates the stacked body in the stacking direction, and is electrically connected at one end to the first semiconductor region. The gate insulating film is arranged between the stacked body and the semiconductor channel. The control circuit supplies a first voltage to a closest conductive film of the stacked body to the first semiconductor region, and supplies a second voltage higher than the first voltage to the first semiconductor region, at a time of reading information from one of memory cells formed at positions where the conductive films intersect with the semiconductor channel.

Abstract: According to one embodiment, there is provided a semiconductor device including a first semiconductor region, a stacked body, a semiconductor channel, a gate insulating film, and a control circuit. The stacked body is of conductive films arranged in a stacking direction with an insulator interposed. The semiconductor channel penetrates the stacked body in the stacking direction, and is electrically connected at one end to the first semiconductor region. The gate insulating film is arranged between the stacked body and the semiconductor channel. The control circuit supplies a first voltage to a closest conductive film of the stacked body to the first semiconductor region, and supplies a second voltage higher than the first voltage to the first semiconductor region, at a time of reading information from one of memory cells formed at positions where the conductive films intersect with the semiconductor channel.

Abstract: A dynamic balancing test and correction apparatus capable of shortening the time required for correcting imbalance in a correction part and improving the entire workflow of the apparatus.

Abstract: A semiconductor memory device includes a conductive layer; a plurality of electrode layers stacked on the conductive layer; a semiconductor pillar extending through the electrode layers in a stacking direction and electrically connected to the conductive layer; and an insulating layer positioned between the semiconductor pillar and the electrode layers and extending along the semiconductor pillar. The semiconductor pillar has a channel portion extending through the electrode layers and a high impurity concentration portion positioned at a bottom end on a side of the conductive layer. The high impurity concentration portion includes an impurity of a higher concentration than an impurity concentration in the channel portion. The insulating layer has an end portion extending toward a center of the bottom end of the semiconductor pillar, and a boundary of the channel portion and the high impurity concentration portion is positioned above the end portion of the insulating layer.

Abstract: An electronic device housing of the present invention is a housing for internally accommodating an electronic device and is provided with a metal bottom plate, and metal side plates folded and integrally connected to the bottom plate, in which, in a metal member (M) formed of at least the bottom plate and the side plate, a thermoplastic resin member is joined to a portion of the surface of the plate-shaped metal member (M), the metal member (M) is reinforced by a thermoplastic resin member, and the thermoplastic resin member is joined to both surfaces of the plate-shaped metal member (M).