Patents by Inventor Shinya Takeda

Shinya Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170230898
    Abstract: A mobile station for receiving broadcast information for restriction control from a base station in a network environment shared by a plurality of operators includes a reception unit configured to receive from the base station the broadcast information including restriction control skip information indicating a type of a call which is not subject to restriction control; and a restriction control determination unit configured to identify restriction control skip information corresponding to an operator with which the mobile station registers from the received broadcast information and determine whether to apply the restriction control.
    Type: Application
    Filed: August 6, 2015
    Publication date: August 10, 2017
    Applicant: NTT DOCOMO, INC.
    Inventors: Wuri Andarmawanti Hapsari, Kenichiro Aoyagi, Shinya Takeda, Yasuharu Konishi
  • Patent number: 9728275
    Abstract: A memory system includes a plurality of pins for connection to the outside of the memory system, one of the pins being configured to receive a command signal, a memory cell array including a plurality of first memory blocks and a second memory block in which status data indicating which of the first memory blocks is defective, is stored, and a control circuit configured to determine whether or not a first memory block targeted by the command signal is indicated as being defective in the status data. The control circuit allows an operation to be performed on the targeted first memory block in accordance with the command signal when the targeted first memory block is not indicated as being defective, and blocks the operation to be performed on the targeted first memory block when the targeted first memory block is indicated as being defective.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 8, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Tsuji, Kenichirou Kada, Shinya Takeda, Toshihiko Kitazume, Shunsuke Kodera, Tetsuya Iwata, Yoshio Furuyama, Hirosuke Narai
  • Publication number: 20170161140
    Abstract: A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
  • Publication number: 20170160946
    Abstract: A memory device includes a semiconductor memory unit, a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, and an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page. The controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not a number of error bits detected by the ECC circuit in the data read from each unit region of the page through the error correction is greater than a predetermined value.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
  • Publication number: 20170160972
    Abstract: A memory system includes a semiconductor memory device including a plurality of blocks, and a controller configured to register a block designated in a protection command as a protected block in a storage region. When the control circuit receives from a host a command to erase the protected block or write to the protected block, the control circuit does not issue a corresponding erase or write command to the semiconductor memory device and notifies the host of the failure to execute the command.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
  • Publication number: 20170152374
    Abstract: A rubber composition for tires according to the present technology comprises: a natural rubber, a diene-based blended rubber containing a solution-polymerized SBR and an emulsion-polymerized SBR, an aromatic modified terpene resin, a silica, and a carbon black. The solution-polymerized SBR contains a specific solution-polymerized SBR having a block containing an isoprene unit at one terminal thereof and a modified terminal for silica at the other terminal thereof. The styrene unit content in the emulsion-polymerized SBR is from 35 to 50 mass %. The content of the natural rubber and the total content of the solution-polymerized SBR and the emulsion-polymerized SBR in the diene-based blended rubber are specified, and the contents of aromatic modified terpene resin, the silica, and the carbon black relative to the content of the diene-based blended rubber are specified.
    Type: Application
    Filed: June 16, 2015
    Publication date: June 1, 2017
    Inventor: Shinya Takeda
  • Publication number: 20170121121
    Abstract: A rotating disk-type preform alignment apparatus 1 including a disk 10, which is rotationally driven about a rotation axis tilted from a vertical direction, and a partition wall 28 erected outwardly of the disk, the apparatus being adapted to align preforms 100, which have been supplied onto the disk, at the peripheral edge of the disk and discharge the aligned preforms from a discharge section, the apparatus comprising: pockets 30 arranged side by side in a circumferential direction at the peripheral edge of the disk, each pocket having an opening portion into which the preform is dropped, and each pocket having a holding portion provided on the inner peripheral surface of the opening portion for holding the preform in an upright state; and a gas jetting unit 40, provided outwardly of the disk between a region where the preforms are supplied onto the disk and the discharge section, for jetting a gas from outside the pocket and from below the pocket, wherein the inner peripheral surface of the opening portion
    Type: Application
    Filed: February 10, 2015
    Publication date: May 4, 2017
    Applicant: NISSEI ASB MACHINE CO., LTD.
    Inventor: Shinya TAKEDA
  • Patent number: 9620230
    Abstract: A memory device includes a semiconductor memory unit, and a controller configured to communicate with a host through a serial interface and access the memory semiconductor unit in response to commands received through the serial interface. The controller, in response to a first read command received through the serial interface to read data in a first page of the semiconductor memory unit, issues a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: April 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takeda, Toshihiko Kitazume, Kenichirou Kada, Nobuhiro Tsuji, Shunsuke Kodera, Tetsuya Iwata, Yoshio Furuyama, Hirosuke Narai
  • Publication number: 20170078949
    Abstract: A user apparatus for use in a mobile communication network that supports a plurality of radio access technologies, including: a reception unit configured, when an origination request transmitted to the mobile communication network from the user apparatus that uses a first radio access technology is rejected, to receive an origination rejection signal including a timer value and an operation instruction from the mobile communication network; and an operation control unit configured to perform inhibition of re-origination based on the timer value included in the origination rejection signal that is received by the reception unit, wherein, in a case where the user apparatus changes a using radio access technology from the first radio access technology to a second radio access technology, the operation control unit determines whether to inhibit re-origination based on the operation instruction included in the origination rejection signal.
    Type: Application
    Filed: May 15, 2015
    Publication date: March 16, 2017
    Applicant: NTT DOCOMO, INC.
    Inventors: Itsuma Tanaka, Shinya Takeda
  • Publication number: 20170060682
    Abstract: A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 2, 2017
    Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
  • Publication number: 20170060484
    Abstract: A memory system includes a semiconductor memory device including a plurality of blocks, and a controller configured to register a block designated in a protection command as a protected block in a storage region. When the control circuit receives from a host a command to erase the protected block or write to the protected block, the control circuit does not issue a corresponding erase or write command to the semiconductor memory device and notifies the host of the failure to execute the command.
    Type: Application
    Filed: February 24, 2016
    Publication date: March 2, 2017
    Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
  • Publication number: 20170062076
    Abstract: A memory system includes a plurality of pins for connection to the outside of the memory system, one of the pins being configured to receive a command signal, a memory cell array including a plurality of first memory blocks and a second memory block in which status data indicating which of the first memory blocks is defective, is stored, and a control circuit configured to determine whether or not a first memory block targeted by the command signal is indicated as being defective in the status data. The control circuit allows an operation to be performed on the targeted first memory block in accordance with the command signal when the targeted first memory block is not indicated as being defective, and blocks the operation to be performed on the targeted first memory block when the targeted first memory block is indicated as being defective.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 2, 2017
    Inventors: Nobuhiro TSUJI, Kenichirou KADA, Shinya TAKEDA, Toshihiko KITAZUME, Shunsuke KODERA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
  • Publication number: 20170062063
    Abstract: A memory device includes a semiconductor memory unit, and a controller configured to communicate with a host through a serial interface and access the memory semiconductor unit in response to commands received through the serial interface. The controller, in response to a first read command received through the serial interface to read data in a first page of the semiconductor memory unit, issues a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 2, 2017
    Inventors: Shinya TAKEDA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shunsuke KODERA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
  • Publication number: 20170060477
    Abstract: A memory device includes a semiconductor memory unit and a controller circuit configured to communicate with a host through a serial interface and access the semiconductor memory unit in response to commands received through the serial interface. The controller circuit, in response to a host command to read parameters of the memory device, updates at least one of parameters of the memory device stored in the memory device based on operational settings of the memory device, and transmits the updated parameters through the serial interface to the host.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 2, 2017
    Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
  • Publication number: 20170062077
    Abstract: A memory system includes a semiconductor memory device, a controller configured to access the semiconductor module, a plurality of pins for connection to the outside of the memory system, the pins configured to receive and output serial data, and a test circuit. When one of the pins receives serial test data, the test circuit converts the serial test data into parallel test data, and outputs the parallel test data to the semiconductor memory device for writing therein, and when the test circuit receives parallel test data written in the semiconductor memory device, the test circuit converts the parallel test data to serial test data, and outputs the serial test data through one of the pins for test of the memory system.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 2, 2017
    Inventors: Kenichirou KADA, Shinya TAKEDA, Toshihiko KITAZUME, Mikio TAKASUGI, Nobuhiro TSUJI, Shunsuke KODERA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
  • Publication number: 20170060676
    Abstract: A memory device includes a semiconductor memory unit, a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, and an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page. The controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not a number of error bits detected by the ECC circuit in the data read from each unit region of the page through the error correction is greater than a predetermined value.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 2, 2017
    Inventors: Shunsuke KODERA, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shinya TAKEDA, Tetsuya IWATA, Yoshio FURUYAMA, Hirosuke NARAI
  • Publication number: 20170062066
    Abstract: A memory system includes first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin, an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first or second chip select signal, and first and second memory cell arrays.
    Type: Application
    Filed: August 10, 2016
    Publication date: March 2, 2017
    Inventors: Hirosuke NARAI, Toshihiko KITAZUME, Kenichirou KADA, Nobuhiro TSUJI, Shunsuke KODERA, Tetsuya IWATA, Yoshio FURUYAMA, Shinya TAKEDA
  • Patent number: 9554364
    Abstract: Provided are a communication system, a mobile station and a communication method that can suppress the increase of processing loads of an IP-CAN accompanying trials made by mobile stations to connect to the IP-CAN via a wireless access network that does not support any services on the IP multimedia core network subsystem (IMS). For example, a UE (100) receives, from an SGSN via the 3G, service non-supporting information indicating that the 3G does not support any services on the IP multimedia subsystem, and, when having received the service non-supporting information, stops the transmission of an Activate PDP Context Request via the 3G.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: January 24, 2017
    Assignee: NTT DOCOMO, INC.
    Inventors: Shinya Takeda, Itsuma Tanaka
  • Patent number: 9538354
    Abstract: The invention provides a mobile communication system, a mobile station, a call control device, and a mobile communication method that are capable of allowing an emergency call, even to which a prefix indicating how to treat the emergency call is added, to break through access control, and applying priority control to the emergency call, as in the case of a normal emergency call without the addition of the prefix. UE (100) separates acquired calling number information into a prefix and a calling number, and sends an MSC (210) an Emergency Setup which includes the prefix and an Emergency Category linked with the calling number. The MSC (210) determines how to treat the emergency call (such as to block notification of a telephone number of a calling party) based on the prefix included in the Emergency Setup, and connects the emergency call to a PSAP (400) corresponding to the Emergency Category.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: January 3, 2017
    Assignee: NTT DOCOMO, INC.
    Inventors: Itsuma Tanaka, Shinya Takeda
  • Patent number: D767371
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: September 27, 2016
    Assignee: HIEN ELECTRIC INDUSTRIES, LTD.
    Inventors: Kazuhisa Matsuo, Shinya Takeda