Patents by Inventor Shinzo Anazawa

Shinzo Anazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4527010
    Abstract: An electronic part mounting construction, such as a transistor package or a substrate for a resin mold device, has a substrate for mounting an electronic part on a principal surface, at least one metallized layer deposited on the principal surface and soldered to the electronic part thereon, another metallized layer continuously extended from the at least one metallized layer in a direction perpendicular thereto, and an insulator layer deposited on the other metallized layer. The other metallized layer is provided on a side surface of a wall member or the substrate. The other metallized layer and the insulator layer may be formed by steps of forming a hole in an insulator sheet, depositing a metallized layer and an insulator layer successively on the surface of the hole, and leaving the metallized layer and the insulator layer at predetermined region(s) by punching the insulator sheet.
    Type: Grant
    Filed: July 30, 1982
    Date of Patent: July 2, 1985
    Assignees: Nippon Electric Co., Ltd., Narumi China Corporation
    Inventors: Shinzo Anazawa, Hitoshi Yamada, Kuniharu Noda, Yasuyuki Fujimoto
  • Patent number: 4340901
    Abstract: An improved brazing structure is disclosed in which at least a tip end portion to be brazed of a lead is bent and this tip end portion is bonded to a metallized layer by a brazing material substantially in perpendicular to the plane of the metallized layer.
    Type: Grant
    Filed: December 21, 1979
    Date of Patent: July 20, 1982
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Shinzo Anazawa, Hideaki Kozu
  • Patent number: 4172261
    Abstract: A semiconductor device is provided with a metal header of a size sufficiently small such that only a semiconductor element holding plate which requires heat dissipation can be mounted thereon. The metal header supports at its upper fringe portion an apertured member having a penetrating opening sealed along the opening. An insulative outer frame having a thermal expansion coefficient of the same order as that of the apertured member is supported on the peripheral portion of the apertured member. A lid member for hermetic sealing is bonded onto the outer frame.
    Type: Grant
    Filed: January 10, 1978
    Date of Patent: October 23, 1979
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Naobumi Tsuzuki, Shinzo Anazawa
  • Patent number: 4067040
    Abstract: A semiconductor device, which provides efficient heat dissipation, includes a semiconductor support member formed of an insulating, thermally conductive material having a projecting portion on the top surface and a first conducting layer extending along the surfaces of the support members from the bottom to the projecting portion. An insulating wall member for installing terminals is disposed on the top surface of the semiconductor support member in areas around the projecting portion. A second conducting layer is formed on the top end face of the wall member, and a hollow portion is provided in the wall member below the second conducting layer.
    Type: Grant
    Filed: December 9, 1976
    Date of Patent: January 3, 1978
    Assignee: Nippon Electric Company, Ltd.
    Inventors: Naobumi Tsuzuki, Shinzo Anazawa, Shozo Noguchi
  • Patent number: 3946428
    Abstract: A semiconductor package device characterized by improved operation at ultra-high frequencies and by improved heat dissipation, includes an auxiliary metal stud mounted on a metal substrate. A semiconductor element, such as a field-effect transistor or bipolar transistor, is mounted on the auxiliary stud and has at least one electrode thereof electrically connected to the stud.
    Type: Grant
    Filed: September 17, 1974
    Date of Patent: March 23, 1976
    Assignee: Nippon Electric Company, Limited
    Inventors: Shinzo Anazawa, Seiichi Ueno, Isamu Nagasako, Tadashi Nawa, Toshiaki Irie, Shigeru Sando
  • Patent number: RE29218
    Abstract: A packaged semiconductor device for use at ultra-high frequencies is characterized by improved high frequency characteristics as a result of reduced stay capacitance and reduced energy loss. The device includes a dielectric substrate and at least two conductor layers each of which is integral and extends over the top, side, and bottom surfaces of the dielectric substrate. No part of the conductor layer on the top surface overlaps the part on the bottom surface when viewed in a direction normal to the substrate.
    Type: Grant
    Filed: October 4, 1976
    Date of Patent: May 10, 1977
    Assignee: Nippon Electric Company, Limited
    Inventors: Shinzo Anazawa, Seiichi Ueno, Isamu Nagasako, Shigeru Sando