Abstract: A ferroelectric memory cell array has 1T/1C memory cells disposed in matrix form. An address storage unit stores threshold memory addresses for dividing the array into a first block for causing each memory cell to store one-bit data for each memory cell and a second block for causing each memory cell pair to store one-bit data for each memory cell pair. An address comparator compares column addresses corresponding to memory addresses with the threshold memory addresses and determines whether each of the memory addresses belongs to either the first or second blocks. An address switching unit controls drivers so that when it is determined that the memory address belongs to the first block, only corresponding word and plate lines are activated and when it is determined that the memory address belongs to the second block, only corresponding word and plate line pairs are activated.

Abstract: A ferroelectric memory, upon reading of a memory cell array, in which the plate line PL is charged to the power supply potential VDD by a driving control circuit prior to driving of the relevant word line WL. The bit lines BL and /BL are charged to the potential VDD by a timing control circuit, then the word line WL is driven. At this time, the lines BL and /BL are discharged by applying an equalizing signal EQ with predetermined pulse width to a reset circuit.

Abstract: The present invention provides a ferroelectric memory capable of arbitrarily dividing a memory block into 1T/1C type and 2T/2C type areas. A memory cell array has 1T/1C type memory cells disposed in matrix form. An address storage unit stores therein threshold memory addresses for dividing the memory cell array into a first block for causing each memory cell to store one-bit data for each memory cell and a second block for causing each memory cell pair to store one-bit data for each memory cell pair. An address comparator compares column addresses corresponding to memory addresses with the threshold memory addresses and determines based on the result of comparison whether each of the memory addresses belongs to either of the first and second blocks.

Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference ?V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.

Abstract: A method for the manufacture of a ferroelectric memory. The ferroelectric memory includes a plurality of memory cells for storing binary data as polarization states of a ferroelectric. The method includes a data writing step of writing those binary data which will be read at a potential level lower than a reference potential level during data reading, to all of the memory cells prior to a heat treatment step.

Abstract: A ferroelectric memory, upon reading of a memory cell array, in which the plate line PL is charged to the power supply potential VDD by a driving control circuit prior to driving of the relevant word line WL. The bit lines BL and /BL are charged to the potential VDD by a timing control circuit, then the word line WL is driven. At this time, the lines BL and /BL are discharged by applying an equalizing signal EQ with predetermined pulse width to a reset circuit.

Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference ?V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.

Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference ?V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.

Abstract: A memory cell array includes ferroelectric memory cells arranged in m rows and n columns, bit lines provided along a row direction, and word lines and plate line provided along a column direction. The word lines are provided side by side so as to intersect each other at the border between the fourth row and fifth row. The arrangement allows the connecting of four ferroelectric memory cells to the same plate line and the same word line. Since the number of ferroelectric memory cells to be accessed simultaneously will be one-half the number of memory cells provided in one row, unnecessary access to the ferroelectric memory cells is reduced, to suppress deterioration of the ferroelectric memory cells. The word lines may instead intersect each other between the second and third lines, so that two ferroelectric memory cells are connected to the same plate and word lines.

Abstract: A method for the manufacture of a ferroelectric memory. The ferroelectric memory includes a plurality of memory cells for storing binary data as polarization states of a ferroelectric. The method includes a data writing step of writing those binary data which will be read at a potential level lower than a reference potential level during data reading, to all of the memory cells prior to a heat treatment step.

Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference ?V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.

Abstract: A memory cell array includes the ferroelectric memory cells arranged in the form of m rows×n columns, bit lines provided along a row direction, and word lines and plate lines provided along a column direction. The word lines are provided side by side so as to intersect each other at the border between fourth row and fifth row. The arrangement allows connecting four ferroelectric memory cells to the same plate line and the same word line. Since the number of ferroelectric memory cells to be accessed simultaneously will be one-half of the number of memory cells provided in one row, unnecessary access to the ferroelectric memory cells can be reduced, thereby deterioration of the ferroelectric memory cells can be suppressed.

Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference ?V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.

Abstract: A memory cell array includes ferroelectric memory cells arranged in the form of m rows and n columns, bit lines provided along a row direction, and word lines and plate lines provided along a column direction. The word lines are provided side by side so as to intersect each other at the border between the fourth row and the fifth row. The arrangement allows the connecting of four ferroelectric memory cells to the same plate line and the same word line. Since the number of ferroelectric memory cells to be accessed simultaneously will be one-half of the number of memory cells provided in one row, unnecessary access to the ferroelectric memory cells can be reduced, thereby deterioration of the ferroelectric memory cells can be suppressed.

Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference &Dgr;V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.

Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference &Dgr;V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.

Abstract: A memory cell array includes the ferroelectric memory cells arranged in the form of m rows×n columns, bit lines provided along a row direction, and word lines and plate lines provided along a column direction. The word lines are provided side by side so as to intersect each other at the border between fourth row and fifth row. The arrangement allows connecting four ferroelectric memory cells to the same plate line and the same word line. Since the number of ferroelectric memory cells to be accessed simultaneously will be one-half of the number of memory cells provided in one row, unnecessary access to the ferroelectric memory cells can be reduced, thereby deterioration of the ferroelectric memory cells can be suppressed.

Abstract: To shorten the time of a test for detecting deteriorated capacitors, a semiconductor memory device having a 2T2C type memory cell structure is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference &Dgr;V between data “0” and data “1” can be made smaller than an operational margin of a sense amplifier. This makes it possible to detect a deteriorated ferroelectric capacitor without conducting a cycling test.

Abstract: A memory device according to the invention has a first pair of bit lines, having first and second bit lines, coupled to a first memory cell which cause a first potential difference between the first and second bit lines; a second pair of bit lines, having third and fourth bit lines, coupled to a second memory cell which causes a second potential difference between the third and fourth bit lines; a first sense amplifier having first and second transistors each of which is a first conductivity type, the gate electrode of said first transistor being connected to said first bit line, the first electrode of the first transistor being connected to the second bit line, the gate electrode of the second transistor being connected to the second bit line, the first electrode of the second transistor being connected to the first bit line; a second sense amplifier having third and fourth transistors each of which is the first conductivity type, the gate electrode of the third transistor being connected to the third bit li

Abstract: A memory device according to the invention has a first pair of bit lines, having first and second bit lines, being coupled to a first memory cell which cause a first potential difference between the first and second bit lines; a second pair of bit lines, having third and fourth bit lines, coupled to a second memory cell which causes a second potential difference between the third and fourth bit lines; a first sense amplifier having first and second transistors each of which is a first conductivity type, the gate electrode of said first transistor being connected to said first bit line, the first electrode of the first transistor being connected to the second bit line, the gate electrode of the second transistor being connected to the second bit line, the first electrode of the second transistor being connected to the first bit line; a second sense amplifier having third and fourth transistors each of which is the first conductivity type, the gate electrode of the third transistor being connected to the third