Patents by Inventor Shirish D. Bahirat

Shirish D. Bahirat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power management
    Patent number: 10146292
    Abstract: The present disclosure includes methods and apparatuses for power management. One method includes transferring data between a memory and a controller via an input/output (I/O) bus, and adjusting an amount of power consumed in association with transferring the data by throttling the I/O bus.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Shirish D. Bahirat
  • POWER MANAGEMENT
    Publication number: 20160342193
    Abstract: The present disclosure includes methods and apparatuses for power management. One method includes transferring data between a memory and a controller via an input/output (I/O) bus, and adjusting an amount of power consumed in association with transferring the data by throttling the I/O bus.
    Type: Application
    Filed: July 6, 2016
    Publication date: November 24, 2016
    Inventor: Shirish D. Bahirat
  • Memory operation power management by data transfer time adjustment
    Patent number: 9405355
    Abstract: The present disclosure includes methods and apparatuses for power management. One method includes transferring data between a memory and a controller via an input/output (I/O) bus, and adjusting an amount of power consumed in association with transferring the data by throttling the I/O bus.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: August 2, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Shirish D. Bahirat
  • POWER MANAGEMENT
    Publication number: 20140059359
    Abstract: The present disclosure includes methods and apparatuses for power management. One method includes transferring data between a memory and a controller via an input/output (I/O) bus, and adjusting an amount of power consumed in association with transferring the data by throttling the I/O bus.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Shirish D. Bahirat
  • WEAR LEVELING MEMORY USING ERROR RATE
    Publication number: 20130346812
    Abstract: The present disclosure relates to wear leveling memory using error rate. A number of embodiments comprise: programming data to a selected group of a number of groups of memory cells based, at least partially, on a process cycle count corresponding to the selected group; determining an error rate corresponding to the selected group; and adjusting the process cycle count corresponding to the selected group based, at least partially, on the determined error rate corresponding to the selected group.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shirish D. Bahirat, Todd A. Marquart