Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

Abstract: In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1?(T2×8000 ?) where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper is removed. The ion stopper does not remain in the interlayer insulating film lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper, and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer. The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

Abstract: A laser annealing apparatus is provided in which laser light is irradiated onto an amorphous semiconductor layer placed inside an annealing chamber through a chamber window, thereby poly-crystallizing the amorphous semiconductor film. Inside the annealing chamber a low degree vacuum (about 1.3×103 Pa to about 1.3 Pa) is maintained at a room temperature. An inert gas such as nitrogen, hydrogen, or argon is introduced into the atmosphere while maintaining the low degree vacuum. As a result, the surface smoothness of the polycrystalline semiconductor layer is comparable to that resulting from high degree vacuum annealing, while, unlike high degree vacuum annealing, there is less contamination of the chamber window and productivity is improved.

Abstract: In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.

Abstract: In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.

Abstract: A thin-film transistor is provided in which the thickness of the insulating film is optimized. A gate electrode is formed on a transparent substrate. A silicon nitride film and a silicon oxide film, acting as a gate insulating film, are formed over the transparent substrate. A polycrystalline silicon film, being a semiconductor film, is formed acting as an active region. A stopper is formed on the polycrystalline silicon film corresponding to the gate electrode. A silicon oxide film and a silicon nitride film, acting as an interlayer insulating film, are deposited as to cover the stopper region. The total film thickness T1 of the stopper and the silicon oxide film is formed to be thinner than (the thickness T2 of the silicon nitride film×8000 Å)½.

Abstract: First through fourth film formation chambers PC1 to PC4 are disposed in the periphery of a transfer chamber TC. If, for example, the ratio of the time required to form gate insulating films to the time required to form the silicon film as a semiconductor film is 1:3, a silicon nitride film and silicon oxide film are formed in the first through third film formation films PC1 to PC3 to become gate insulating films, and an amorphous silicon layer is formed in the fourth film formation chamber PC4 to become an active region. This makes it possible to perform formation of the amorphous silicon layer, which requires film cleaning, in a film formation chamber different from the film formation chamber for other films, and to manufacture thin-film transistors at high productivity.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

Abstract: On a substrate, there is disposed a gate electrode having a section of a trapezoidal configuration expanded toward the substrate. The gate electrode is covered with a silicon nitride film having a thickness T1 of 400 Å, and a silicon oxide film having a thickness T2 of 1200 Åis formed on the silicon nitride film. A polycrystalline silicon film constructing an active region is formed on a gate insulating film constituted of the silicon nitride film and the silicon oxide film. By forming the silicon oxide film in a sufficient thickness of 1200 Åor more, and further forming the silicon nitride film 23 of 400 Åor more, a thin-film transistor cannot easily be influenced by a stepped portion formed by the gate electrode, and withstanding voltage of the gate insulating film of the thin-film transistor can be enhanced.

Abstract: A laser annealing apparatus is provided in which laser light is irradiated onto an amorphous semiconductor layer placed inside an annealing chamber (100) through a chamber window (120), thereby poly-crystallizing the amorphous semiconductor film. Inside the annealing chamber 100 a low degree vacuum (about 1.3×103 Pa to about 1.3 Pa) is maintained at a room temperature. An inert gas such as nitrogen, hydrogen, or argon is introduced into the atmosphere while maintaining the low degree vacuum. As a result, the surface smoothness of the polycrystalline semiconductor layer is comparable to that resulting from high degree vacuum annealing, while, unlike high degree vacuum annealing, there is less contamination of the chamber window (120) and productivity is improved.

Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.

Abstract: In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.

Abstract: On a substrate, there is disposed a gate electrode having a section of a trapezoidal configuration expanded toward the substrate. The gate electrode is covered with a silicon nitride film having a thickness T1 of 400 Å, and a silicon oxide film having a thickness T2 of 1200 Åis formed on the silicon nitride film. A polycrystalline silicon film constructing an active region is formed on a gate insulating film constituted of the silicon nitride film and the silicon oxide film. By forming the silicon oxide film in a sufficient thickness of 1200 Åor more, and further forming the silicon nitride film 23 of 400 Åor more, a thin-film transistor cannot easily be influenced by a stepped portion formed by the Ls gate electrode, and withstanding voltage of the gate insulating film of the thin-film transistor can be enhanced.

Abstract: On a transparent substrate where a gate electrode is formed, an amorphous silicon film is deposited by plasma CVD with a gate insulating film interposed therebetween. The silicon film is heated in an nitrogen atmosphere at 430±20° C. for an hour or longer to discharge hydrogen remaining in the film when it is formed. The silicon film is then melted by laser irradiation to crystallize, to thereby form a polycrystalline silicon film serving as an active region. Thus, when amorphous silicon is crystallized to form a polycrystalline silicon film, it is made possible to prevent creation of a rough film surface and penetration of impurity ions in the atmosphere into the polycrystalline silicon.

Abstract: On a transparent substrate, on which is positioned a gate electrode, a silicon nitride film and a silicon oxide film are formed as gate insulating films, and furthermore a polycrystalline silicon film is formed as a semiconductor film to become an active region. A stopper is positioned on the polycrystalline silicon film to correspond to a gate electrode, and a silicon oxide film, a silicon nitride film, and a silicon oxide film are formed as interlayer insulating film so as to cover the stopper. Contact holes are formed in the layer insulating film to correspond to a source region and a drain region, and a source electrode and a drain electrode are positioned through these contact holes.