Abstract: An ISDN communication controller or a multi-circuit communication controller is implemented in a sheet of communication adapter board. For each channel or circuit, a dedicated subprocessor section conducts communication processing. In each subprocessor section, a local bus is disposed to connect a CPU, a serial controller, and an RAM. In a main processor section controlling the subprocessors, a local bus is employed to connect a CPU, an RAM, and an ROM. In a system processor section exclusively achieving information processing, a system bus is used to connect a CPU and a main memory. The local buses are connected via respective controllers to an upper-level local bus. A shared RAM is connected via a controller to the upper-level local bus and the system bus. The controllers of the subprocessor sections translate addresses to be outputted from the main processor section to the upper-level local bus to supply translated addresses to the respective local bus.

Abstract: A terminal controller detects state of a plurality of terminal devices by polling system, and the detected state is in a terminal management table possessed by the terminal controller and each terminal device, and the communication processing is performed corresponding to the table content. The terminal controller and each terminal device comprise respectively a main processor connected through a bus to a main memory and a communication control adapter. The communication control adapter is composed of a local processor, a local memory and a communication data send/receive circuit, and terminal management table region is provided on the main memory and the local memory. The local processor executes management of the terminal management table, and rewrites the terminal management information on the local memory and at the same time transfers the terminal management information onto the main memory by the DMA function provided on the communication control adapter.

Abstract: A data proessing system includes a processor, a memory, a direct memory accessing (DMA) control unit and an input/output adapter. A memory area of a given capacity is reserved in the memory for storing control information transferred between the processor and the adapter. For transfer of the control information, the adapter accesses the control information stored in the memory area through direct memory accessing under control of the DMA control unit while the processor can make access to the control information through a memory read/write command. By storing at the predetermined area of the memory the control information transferred between the processor and the adapter, the quantity of hardware and the number of IC's required for implementing the adapter can be significantly reduced. Conflicting access requests to the main memory area by the processor and adapter are prevented through time-division control of the memory bus.