Patents by Inventor Shiro Uchiyama
Shiro Uchiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955461Abstract: Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.Type: GrantFiled: August 24, 2021Date of Patent: April 9, 2024Assignee: Micron Technology, Inc.Inventor: Shiro Uchiyama
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Publication number: 20230215828Abstract: Layouts for data pads on a semiconductor die are disclosed. An apparatus may include circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The apparatus may also include data pads variously electrically coupled to the circuits. The data pads may include a data pad positioned a first distance from the first edge and a second distance from the second edge. The apparatus may also include dummy data pads electrically isolated from the circuits. The dummy data pads may include a dummy data pad positioned substantially the first distance from the first edge and substantially the second distance from the fourth edge. Associated systems and methods are also disclosed.Type: ApplicationFiled: August 31, 2022Publication date: July 6, 2023Inventors: Andreas Kuesel, Takamasa Suzuki, Jens Polney, Seiji Narui, Shiro Uchiyama
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Publication number: 20230065325Abstract: A semiconductor device assembly including a first semiconductor wafer having a first side and a second side opposite the first side, the first semiconductor wafer including: a first plurality of semiconductor devices at the first side, a plurality of non-metallic vias extending from the second side towards the first side, and a plurality of alignment marks, each vertically aligned with a corresponding one or more of the plurality of non-metallic vias, a second semiconductor wafer including a second plurality of semiconductor devices and a plurality of registration marks, each of the plurality of registration marks vertically aligned with a corresponding one or more of the plurality of alignment marks.Type: ApplicationFiled: January 31, 2022Publication date: March 2, 2023Inventors: Shiro Uchiyama, Eiichi Nakano
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Publication number: 20230062701Abstract: Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.Type: ApplicationFiled: August 24, 2021Publication date: March 2, 2023Inventor: Shiro Uchiyama
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Patent number: 11380665Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.Type: GrantFiled: August 28, 2019Date of Patent: July 5, 2022Assignee: Micron Technology, Inc.Inventors: Eiichi Nakano, Shiro Uchiyama
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Patent number: 10896875Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.Type: GrantFiled: October 1, 2019Date of Patent: January 19, 2021Assignee: Micron Technology, Inc.Inventor: Shiro Uchiyama
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Patent number: 10600770Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.Type: GrantFiled: May 14, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Eiichi Nakano, Shiro Uchiyama
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Publication number: 20200035597Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.Type: ApplicationFiled: October 1, 2019Publication date: January 30, 2020Applicant: MICRON TECHNOLOGY, INC.Inventor: Shiro Uchiyama
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Publication number: 20190385996Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.Type: ApplicationFiled: August 28, 2019Publication date: December 19, 2019Inventors: Eiichi Nakano, Shiro Uchiyama
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Publication number: 20190348406Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.Type: ApplicationFiled: May 14, 2018Publication date: November 14, 2019Inventors: Eiichi Nakano, Shiro Uchiyama
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Patent number: 10438888Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.Type: GrantFiled: June 5, 2018Date of Patent: October 8, 2019Assignee: Micron Technology, Inc.Inventor: Shiro Uchiyama
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Publication number: 20180301408Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.Type: ApplicationFiled: June 5, 2018Publication date: October 18, 2018Applicant: Micron Technology, Inc.Inventor: Shiro Uchiyama
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Patent number: 9997452Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.Type: GrantFiled: January 27, 2017Date of Patent: June 12, 2018Assignee: Micron Technology, Inc.Inventor: Shiro Uchiyama
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Patent number: 8937390Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: GrantFiled: March 6, 2014Date of Patent: January 20, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
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Publication number: 20140183730Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: ApplicationFiled: March 6, 2014Publication date: July 3, 2014Inventors: Nae HISANO, Shigeo OHASHI, Yasuo OSONE, Yasuhiro NAKA, Hiroyuki TENMEI, Kunihiko NISHI, Hiroaki IKEDA, Masakazu ISHINO, Hideharu MIYAKE, Shiro UCHIYAMA
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Patent number: 8722502Abstract: A method of manufacturing a semiconductor device, includes forming a trench surrounding a first area of a semiconductor substrate, the trench having a bottom surface and two side surfaces being opposite to each other, forming a silicon film on the bottom surface and side surfaces of the trench, forming an insulation film on the silicon film in the trench, grinding a bottom surface of the semiconductor substrate to expose the insulation film formed over the bottom surface of the trench, and forming a through electrode in the first area after grinding the bottom surface of the semiconductor substrate, the through electrode penetrating the semiconductor substrate.Type: GrantFiled: April 13, 2011Date of Patent: May 13, 2014Inventor: Shiro Uchiyama
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Patent number: 8704352Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.Type: GrantFiled: January 6, 2010Date of Patent: April 22, 2014Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
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Patent number: 8536711Abstract: A semiconductor device includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a first silicon film in contact with an inner surface of the isolation trench, a second silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the first and second silicon films.Type: GrantFiled: April 13, 2011Date of Patent: September 17, 2013Assignee: Elpida Memory, Inc.Inventor: Shiro Uchiyama
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Patent number: 8334465Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.Type: GrantFiled: September 30, 2008Date of Patent: December 18, 2012Assignee: Elpida Memory, Inc.Inventors: Masakazu Ishino, Hiroaki Ikeda, Hideharu Miyake, Shiro Uchiyama, Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano
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Patent number: 8004090Abstract: A first insulating layer including a first contact pad made of conductive polysilicon and a second insulating layer including a second contact pad are formed over a semiconductor silicon layer. After this, a via hole for a through-hole electrode is formed until the via hole penetrates through at least the semiconductor silicon layer and the first contact pad and reaches to the second contact pad.Type: GrantFiled: October 27, 2008Date of Patent: August 23, 2011Assignee: Elpida Memory, IncInventor: Shiro Uchiyama