Patents by Inventor Shiroo Kamohara

Shiroo Kamohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5742071
    Abstract: A logical operation circuit in which wiring as generally performed between transistors is made unnecessary to improve reliability, stability and integration degree of a logical circuit using a tunnel phenomenon, for example, a single-electron tunnel phenomenon, or a flight phenomenon of a particle group. Conducting materials are arranged in a two-dimensional plane or three-dimensional space in the logical circuit. When two conducting materials are arranged to be nearest each other, the two conducting materials are connected, for example, by a single-electron tunnel phenomenon. When two conducting materials are arranged to be not nearest, there is no connection between the conducting materials by the tunnel phenomenon. Propagation of electrons is controlled by changing the arrangement.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: April 21, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Shiroo Kamohara, Peter M. Lee, Hitoshi Matsuo, Sigeo Ihara
  • Patent number: 5422496
    Abstract: An interband single-electron tunnel/transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: June 6, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shiroo Kamohara, Toru Toyabe, Kozo Katayama, Shuichi Yamamoto, Sigeo Ihara
  • Patent number: 5323344
    Abstract: A quantum memory device in which a memory operation is enabled even if the structure of a Josephson device is reduced in size. Each memory cell of the quantum memory device includes a superconducting quantum interference device having two Josephson junctions, a write word line for supplying a current to the superconducting quantum interference device, a write data line and a magnetic field detection line magnetically coupled with the superconducting quantum interference device, a three-terminal switching device for turning a signal of the magnetic field detection line on and off to transfer the signal to a read data line, and a read word line connected to a gate of the three-terminal switching device. The junction area of the Josephson junction is made small to oscillate a magnetic flux so that information is stored in accordance with the phase of oscillation of the magnetic flux.
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: June 21, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kozo Katayama, Shiroo Kamohara
  • Patent number: 5258625
    Abstract: An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: November 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Shiroo Kamohara, Toru Toyabe, Kozo Katayama, Shuichi Yamamoto, Sigeo Ihara