Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.

Abstract: A system can maintain information indicative of prohibited computer operations, wherein the information is accessible to respective computing clusters of a group of computing clusters, and wherein the information is stored separately from the group of computing clusters. The system can obtain, by a service of a first computing cluster of the group of computing clusters, the information. The system can, in response to receiving, at the first computing cluster, a request to perform an operation on a first computer of the first computing cluster, in response to determining, based on the information, that the operation is prohibited, prevent the operation from occurring; and, in response to determining, based on the information, that the operation is not prohibited, permit the operation to occur.

Abstract: An archival job is assessed to calculate loss of data reduction efficiency due to block-level data deduplication. Archivable data, or individual storage objects or data structures therein, are moved to archival storage contingent upon satisfaction of a predetermined condition related to data reduction efficiency. Archivable data, or individual storage objects or data structures therein, that fail to satisfy the predetermined condition are maintained in primary storage. The loss of data reduction efficiency and the predetermined condition may be expressed as a percentage of maximum possible data reduction that would result in the absence of data deduplication.

Abstract: A system comprising an air intake structure, a tunnel structure, and an energy generation device is described. The air intake structure may include a first entrance and a first exit. The air intake structure may receive air directed towards the first entrance. A size difference between the first entrance and the first exit may cause a compression of the received air into first compressed air. The tunnel structure may include a second entrance and a second exit. The tunnel structure may receive the first compressed air. A size difference between the second entrance and the second exit may cause a compression of the first compressed air into second compressed air. The energy generation device may receive the second compressed air, and may transform a portion of the second compressed air into energy. The system may further include elements effective to facilitate cooling of components of a vehicle.

Abstract: A system comprising an air intake structure, a tunnel structure, and an energy generation device is described. The air intake structure may include a first entrance and a first exit. The air intake structure may receive air directed towards the first entrance. A size difference between the first entrance and the first exit may cause a compression of the received air into first compressed air. The tunnel structure may include a second entrance and a second exit. The tunnel structure may receive the first compressed air. A size difference between the second entrance and the second exit may cause a compression of the first compressed air into second compressed air. The energy generation device may receive the second compressed air, and may transform a portion of the second compressed air into energy. The system may further include elements effective to facilitate cooling of components of a vehicle.

Abstract: Impedance detection methods and systems are presented for automatic computation of an electrical component impedance value at one or more specific frequencies of interest using quadrature voltage and current values generated by quadrature tracking filters based on sensed or measured voltage and current signals or values and a base frequency input.

Abstract: Impedance detection methods and systems are presented for automatic computation of an electrical component impedance value at one or more specific frequencies of interest using quadrature voltage and current values generated by quadrature tracking filters based on sensed or measured voltage and current signals or values and a base frequency input.

Abstract: The invention relates to a chemically synthesised artificial promoter comprising a DNA sequence designed for the target level and pattern of gene expression, by strategically putting together several signature sequences identified by sequence alignment and statistical analysis of a large database constructed for this purpose.

Abstract: Described herein is the usage of a digital input/output card as an MPEG transport stream. A transport stream feeder for verifying a video decoder is presented. The transport stream feeder comprises a digital input/output card. The digital input/output card comprises a first memory, a processor, and a second memory. The first memory stores a reference video. The processor encodes the reference video. The second memory stores a decoded reference video, the decoded reference video decoded by the video decoder.

Abstract: Presented herein is a system, method, and apparatus for firmware code-coverage in complex system on chip. A circuit for analyzing code coverage of firmware by test inputs comprises an input and a memory. The input receives an address from a code address bus. The memory stores recorded addresses from the code address bus. The memory comprises a plurality of memory locations, each of the memory locations mapped to a particular one of a corresponding plurality of addresses associated with the firmware. The contents of the memory location associated with the address received from the code address bus being incremented responsive to receipt of the address.

Abstract: Described herein are parallel instances of a plurality of systems on chip in a hardware emulator verification. Significant amount of product cycle time is saved by verifying systems on chip in a parallel fashion in contrast to serial fashion.