Patents by Inventor Shiva Prasad Kotagiri
Shiva Prasad Kotagiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230299779Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for implementing a SAR ADC circuit with improved quantization error. In some implementations, an apparatus includes an analog-to-digital converter (ADC) configured to receive a set of voltage signals and generate digital representations of signals. The ADC comprises a capacitive digital-to-analog converter (CDAC) comprising a capacitive divider circuit, the capacitive divider circuit comprising (i) a first capacitor in parallel with a second capacitor in a first branch, (ii) a plurality of capacitors in a plurality of other respective branches, and (iii) the CDAC configured to receive the set of sampled voltages and adjust each set of the sampled voltages by a first voltage or a second voltage through selection of one or more capacitors of the (i) first capacitor and the second capacitor and (ii) one or more of the plurality of capacitors.Type: ApplicationFiled: January 13, 2023Publication date: September 21, 2023Inventors: Shiva Prasad Kotagiri, Fu-Tai An
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Publication number: 20180302264Abstract: An integrated circuit for supporting a high-speed communications link. The integrated circuit may include equalization and hybrid phase detection circuitry configured to perform clock data recovery (CDR) for high-order pulse amplitude modulated (PAM) signals. The phase detector circuit includes partial oversampling sampling circuitry that generates edge samples an incoming PAM signal and Baud rate sampling circuitry that generates error and data samples on the PAM signals. Edge, data, and error samples may be passed to error minimization circuitry within an adaptation circuit that may dynamically compute contributions to a weighted phase error by oversampling and Baud rate components. The adaptation circuit may use the weighted phase error to adjust the phase of a recovered clock signal used to recover data transmitted through the high speed communications link.Type: ApplicationFiled: April 17, 2017Publication date: October 18, 2018Applicant: Intel CorporationInventors: Yu Liao, Wenyi Jin, Shiva Prasad Kotagiri, Jihong Ren
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Patent number: 9397674Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.Type: GrantFiled: December 31, 2013Date of Patent: July 19, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Pervez M. Aziz, Shiva Prasad Kotagiri, Sundeep Venkatraman, Sunil Srinivasa, Amaresh V. Malipatil
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Patent number: 9306775Abstract: A receiver disposed in a serializer/deserializer (SerDes) system includes a coupling capacitor configured to receive a serial input signal from a transmitter operatively coupled with the receiver via a communication channel established therebetween and to output a capacitance output signal, an equalizer configured to receive a signal including the capacitance output signal having a baseline wander gain subtracted therefrom, a running disparity generator receiving decoded symbols and generating a running disparity signal, and a low-pass filter receiving the running disparity signal and outputting the BLW gain.Type: GrantFiled: September 11, 2014Date of Patent: April 5, 2016Inventors: Shiva Prasad Kotagiri, Amaresh V. Malipatil
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Publication number: 20160080176Abstract: A receiver disposed in a serializer/deserializer (SerDes) system includes a coupling capacitor configured to receive a serial input signal from a transmitter operatively coupled with the receiver via a communication channel established therebetween and to output a capacitance output signal, an equalizer configured to receive a signal including the capacitance output signal having a baseline wander gain subtracted therefrom, a running disparity generator receiving decoded symbols and generating a running disparity signal, and a low-pass filter receiving the running disparity signal and outputting the BLW gain.Type: ApplicationFiled: September 11, 2014Publication date: March 17, 2016Inventors: Shiva Prasad Kotagiri, Amaresh V. Malipatil
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Publication number: 20150381393Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.Type: ApplicationFiled: June 26, 2014Publication date: December 31, 2015Inventors: Shiva Prasad Kotagiri, Pervez M. Aziz, Amaresh V. Malipatil
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Patent number: 9106370Abstract: A method for facilitating acquisition of a received reference clock signal in a CDR system includes steps of: initializing an integral register in a digital loop filter of the CDR system by setting a current value of the integral register to a first value; determining a number of mislock events occurring in a CDR loop of the CDR system, a mislock event being indicative of an unlocked state of the CDR loop; adjusting the current value of the integral register, when the number of mislock events is non-zero, by a second value to generate a new current value, the second value being a function of a negation of the current value of the integral register; and repeating the steps of determining the number of mislock events and adjusting the current value of the integral register until the number of mislock events is zero.Type: GrantFiled: September 25, 2014Date of Patent: August 11, 2015Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Sunil Srinivasa, Amaresh V. Malipatil, Mohammad Shafiul Mobin, Pervez Mirza Aziz, Shiva Prasad Kotagiri
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Publication number: 20150188551Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.Type: ApplicationFiled: December 31, 2013Publication date: July 2, 2015Applicant: LSI CorporationInventors: Pervez M. Aziz, Shiva Prasad Kotagiri, Sundeep Venkatraman, Sunil Srinivasa, Amaresh V. Malipatil
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Publication number: 20150103961Abstract: A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (CDR) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the CDR. Output signals from the moving average filters are processed to determine a half-wave time period for each output signal by measuring the number clock cycles occurring between transitions of each output signal. The number of clock cycles of the longest half-wave period is compared to multiple values representing frequency limits of various frequency bands to determine which frequency band to classify jitter the gain-controlled signal. The determined frequency band is used to select from a look-up table a set of gain values for use in the CDR.Type: ApplicationFiled: October 14, 2013Publication date: April 16, 2015Applicant: LSI CorporationInventors: Amaresh V. Malipatil, Shiva Prasad Kotagiri, Sundeep Venkatraman, Sunil Srinivasa, Pervez M. Aziz
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Patent number: 8989254Abstract: An apparatus includes a first coding circuit, a second coding circuit, and a plurality of source series terminated driver slices. The first coding circuit may be configured to generate a plurality of digital filter control codes in response to a plurality of filter coefficients and a control signal. The control signal selects between a plurality of communication specifications. The second coding circuit may be configured to generate a plurality of driver slice control codes in response to the plurality of digital filter control codes. The plurality of source series terminated driver slices configured to generate an output signal according to a selected one of the plurality of communication specifications in response to the plurality of driver slice control codes, a main cursor signal, a pre-cursor signal, and a post cursor signal.Type: GrantFiled: March 27, 2013Date of Patent: March 24, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Tai Jing, Lijun Li, Shiva Prasad Kotagiri
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Patent number: 8831142Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.Type: GrantFiled: December 18, 2012Date of Patent: September 9, 2014Assignee: LSI CorporationInventors: Shiva Prasad Kotagiri, Pervez M. Aziz, Amaresh V. Malipatil
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Publication number: 20140181845Abstract: An apparatus includes a first coding circuit, a second coding circuit, and a plurality of source series terminated driver slices. The first coding circuit may be configured to generate a plurality of digital filter control codes in response to a plurality of filter coefficients and a control signal. The control signal selects between a plurality of communication specifications. The second coding circuit may be configured to generate a plurality of driver slice control codes in response to the plurality of digital filter control codes. The plurality of source series terminated driver slices configured to generate an output signal according to a selected one of the plurality of communication specifications in response to the plurality of driver slice control codes, a main cursor signal, a pre-cursor signal, and a post cursor signal.Type: ApplicationFiled: March 27, 2013Publication date: June 26, 2014Applicant: LSI CorporationInventors: Tai Jing, Lijun Li, Shiva Prasad Kotagiri
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Publication number: 20140169440Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for dock recovery.Type: ApplicationFiled: December 18, 2012Publication date: June 19, 2014Applicant: LSI CORPORATIONInventors: Shiva Prasad Kotagiri, Pervez M. Aziz, Amaresh V. Malipatil