Abstract: The present disclosure relates to a drive circuit, including: a first module, generating display data based on image information; a second module, generating a display signal based on the display data and a plurality of clock signals; a third module, outputting a constant current based on the display signal; and a fourth module, configured to provide a reference current to the third module, wherein the fourth module includes: a reference voltage generation module, a bias module, a current generation module, and a pre-charging module. Any two adjacent clock signals of the plurality of clock signals differ by M complete clock cycles, where 0?M<1. This circuit can realize relatively high image display accuracy with relatively low system power consumption and chip cost, and meanwhile realize effective low grayscale compensation for image.

Abstract: The present disclosure relates to a drive circuit, including: a first module, generating display data based on image information; a second module, generating a display signal based on the display data and a plurality of clock signals; a third module, outputting a constant current based on the display signal; and a fourth module, configured to provide a reference current to the third module, wherein the fourth module includes: a reference voltage generation module, a bias module, a current generation module, and a pre-charging module. Any two adjacent clock signals of the plurality of clock signals differ by M complete clock cycles, where 0?M<1. This circuit can realize relatively high image display accuracy with relatively low system power consumption and chip cost, and meanwhile realize effective low grayscale compensation for image.

Abstract: The present disclosure relates to a constant current source calibration circuit, a constant current source drive circuit, a drive chip, and an electronic device. The current calibration circuit includes a resistor and a calibration circuit connected to the resistor for adjusting a voltage drop across two ends of the resistor; and a selector or a switch connected to the two ends of the resistor, and configured to select one end of the resistor to be connected to a constant current source output channel and the corresponding other end to be supplied with a first bias voltage VD. Since the first bias voltage VD is a fixed constant, the voltage drop across the two ends of the resistor is adjusted.

Abstract: A memory controller scrambles input data and stores the scrambled data in a memory, and then allows the stored data to be read from the memory only once. The memory controller includes a true random number generator (TRNG) for generating a true random number and a pseudo-random number generator (PRNG) that uses the true random number as a seed to generate a pseudo-random number. A linear feedback shift register (LFSR) receives and shifts the pseudo-random number and then scrambles the input data using the shifted number from the LFSR. The scrambled data then is stored in the memory and the seed is stored in one of the same or a separate memory. In response to a read request, the seed is read and used to regenerate the shifted number to descramble the stored data. The stored seed is invalidated to prevent additional attempts at reading the data.

Abstract: In a System on a Chip (SOC) having multiple masters and multiple slaves connected to a bus via a crossbar switch, a time-based secure access control system of the SOC includes a central access control (CAC) circuit coupled to the master devices through respective channels to receive time-based access requests from the masters. Each slave is connected to a slave access control (SAC) circuit and each SAC circuit includes an access time control (ATC) circuit in communication with the CAC circuit and a dedicated timer. The CAC circuit controls the ATC circuits to limit the access permission from the masters to the slaves by checking whether a requested access time has expired.

Abstract: In a System on a Chip (SOC) having multiple masters and multiple slaves connected to a bus via a crossbar switch, a time-based secure access control system of the SOC includes a central access control (CAC) circuit coupled to the master devices through respective channels to receive time-based access requests from the masters. Each slave is connected to a slave access control (SAC) circuit and each SAC circuit includes an access time control (ATC) circuit in communication with the CAC circuit and a dedicated timer. The CAC circuit controls the ATC circuits to limit the access permission from the masters to the slaves by checking whether determining whether a requested access time has expired.

Abstract: A memory controller scrambles input data and stores the scrambled data in a memory, and then allows the stored data to be read from the memory only once. The memory controller includes a true random number generator (TRNG) for generating a true random number and a pseudo-random number generator (PRNG) that uses the true random number as a seed to generate a pseudo-random number. A linear feedback shift register (LFSR) receives and shifts the pseudo-random number and then scrambles the input data using the shifted number from the LFSR. The scrambled data then is stored in the memory and the seed is stored in one of the same or a separate memory. In response to a read request, the seed is read and used to regenerate the shifted number to descramble the stored data. The stored seed is invalidated to prevent additional attempts at reading the data.

Abstract: A device for secure data storage has a host unit that obtains data stored on an external device at an external storage address; a user signal generator that generates a user defined security signal based on the external storage address of the data that indicates a security level of the data; a storage address determining unit that determines an internal storage address for the data based on the security level of the data; and a storage unit that stores the data at the internal storage address corresponding to the security level.

Abstract: A monitor fixing mechanism for fixing a monitor is disclosed. The monitor fixing structure includes a pivot plate and a support member. The pivot plate is detachably connected to the support plate so as to pivot the monitor relative to a stand. The support member includes a plate, at least one lateral guiding structure disposed on the plate for laterally constraining movement of the pivot plate as the pivot plate is sliding into the plate in a first direction, and at least one stopping structure disposed on the plate for stopping an end of the pivot plate as the pivot plate has slid into the plate in the first direction completely. The monitor fixing mechanism further includes a fastening module for fastening the pivot plate on the support member as the pivot plate has slid into the plate in the first direction completely.

Abstract: A monitor fixing mechanism for fixing a monitor is disclosed. The monitor fixing structure includes a pivot plate and a support member. The pivot plate is detachably connected to the support plate so as to pivot the monitor relative to a stand. The support member includes a plate, at least one lateral guiding structure disposed on the plate for laterally constraining movement of the pivot plate as the pivot plate is sliding into the plate in a first direction, and at least one stopping structure disposed on the plate for stopping an end of the pivot plate as the pivot plate has slid into the plate in the first direction completely. The monitor fixing mechanism further includes a fastening module for fastening the pivot plate on the support member as the pivot plate has slid into the plate in the first direction completely.