Abstract: A blocking signal cancellation low noise amplifier system includes a first low noise amplifier, a second low noise amplifier, a blocking signal extraction and bias generation circuit, a bias switching circuit, and a bias switching signal generating circuit. The first low noise amplifier is used for dynamic input matching, and the first low noise amplifier receives an input signal and outputs it after amplifying. The blocking signal extraction and bias generation circuit is used to extract a blocking signal from the output signal of the first low noise amplifier, and output a DC voltage signal. The bias switching circuit is used to switch the first low noise amplifier between a blocking mode and a small signal mode. The bias switching signal generating circuit is used to compare the DC bias voltage signal VB2 with a preset reference voltage signal Vref.

Abstract: A blocking signal cancellation low noise amplifier system includes a first low noise amplifier, a second low noise amplifier, a blocking signal extraction and bias generation circuit, a bias switching circuit, and a bias switching signal generating circuit. The first low noise amplifier is used for dynamic input matching, and the first low noise amplifier receives an input signal and outputs it after amplifying. The blocking signal extraction and bias generation circuit is used to extract a blocking signal from the output signal of the first low noise amplifier, and output a DC voltage signal. The bias switching circuit is used to switch the first low noise amplifier between a blocking mode and a small signal mode. The bias switching signal generating circuit is used to compare the DC bias voltage signal VB2 with a preset reference voltage signal Vref.

Abstract: A Phase-Locked Loop (PLL) has a multi-curve voltage-controlled oscillator (VCO) with a curve-select input that adjusts the capacitance within the VCO and thus the VCO gain. A calibration unit generates a curve-select value to the VCO. Coarse calibration selects a Center Curve CC value using binary search of the curve-select bits. During fine calibration, the number of pulses of the VCO output are counted and stored for all curves in a target window around the center curve. The stored pulse counts are compared to an ideal pulse count for a specified frequency, and the curve-select value for the closest-matching pulse count is applied to the VCO. The target window is much smaller than all possible curves, so calibration is performed only on a few curves, reducing calibration time. A switch before the VCO opens the loop for faster open-loop calibration. Pulses are counted digitally without expensive analog comparators.

Abstract: A two-point modulation Phase-Locked Loop (PLL) has a gain-adjustable voltage-controlled oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to a Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. A calibration unit divides the VCO output and counts pulses. During calibration, the data modulation signal is set to minimum and then maximum values and VCO output pulses counted. A count difference for the data modulation signal at maximum and minimum values is input to a Look-Up Table (LUT) to read out a gain calibration value. During normal operation mode, the gain calibration value from the LUT is applied to a second input of the DAC, which drives the VCO to adjust VCO gain. A switch before the VCO opens the loop for faster open-loop calibration.

Abstract: Even harmonics are suppressed by a harmonics-reducing bias generator that drives bias voltages to cascode control transistors in series with driver transistors in a power amplifier. A first bias voltage is generated by mirroring pull-up currents in the power amplifier. A p-channel source transistor and a p-channel cascode current-mirror transistor also mirror the power amplifier pull-up current to a midpoint node. An n-channel sink transistor and an n-channel cascode current-mirror transistor mirror the pull-down current in the power amplifier to the midpoint node. An op amp compares the midpoint node to VDD/2, and drives the gate of a p-channel feedback transistor. Current from the p-channel feedback transistor flows through an n-channel cascode current-mirror transistor that generates a second bias voltage. The second bias voltage is adjusted until the midpoint node reaches VDD/2, causing the pull-up and pull-down currents in the power amplifier to better match, reducing even harmonics.

Abstract: A multi-stage Successive-Approximation Register (SAR) pipeline Analog-to-Digital Converter (ADC) has an amplifier between two switched capacitor networks, each controlled by a SAR. The load capacitance of the amplifier is magnified due to the amplifier's gain. This magnified load capacitance can disproportionately increase power consumption. The back plates of the second-stage switched capacitors are connected to the amplifier input using a feedback switch during an amplification phase, so that the second-stage switched capacitors are connected between the input and output of the amplifier as a feedback capacitor, rather than a load capacitor. Reset switches are added to drive both plates of the second-stage switched capacitors to ground during a reset phase before the amplification phase. Thus the second-stage switched capacitors function as both the feedback capacitor and as the switched capacitors controlled by the second SAR.

Abstract: A mesh bag including warp and weft thread groups and a closing part, wherein the warp groups are arranged crosswise, and the weft groups are laid out intersecting with the warp groups, starting from the junctions of the warp group, the warp group goes through the perforation of weft loop, the knitting threads of the warp groups go through the outermost weft loop and then are knitted crosswise to form the mesh hole, and the closing part is formed through mesh holes being closed at the terminal end. The entire warp thread is knitted throughout the mesh bag, which can solve the existing technical problem that the mesh thread bears uneven stress so as to allow the stress on the entire warp thread to be distributed equally and therefore to increase the loading capacity of the mesh bag.

Abstract: A mesh bag including warp and weft thread groups and a closing part, wherein the warp groups are arranged crosswise, and the weft groups are laid out intersecting with the warp groups, starting from the junctions of the warp group, the warp group goes through the perforation of weft loop, the knitting threads of the warp groups go through the outermost weft loop and then are knitted crosswise to form the mesh hole, and the closing part is formed through mesh holes being closed at the terminal end. The entire warp thread is knitted throughout the mesh bag, which can solve the existing technical problem that the mesh thread bears uneven stress so as to allow the stress on the entire warp thread to be distributed equally and therefore to increase the loading capacity of the mesh bag.