Patents by Inventor Shizuo Gotou

Shizuo Gotou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5151991
    Abstract: In order to make parallel processing of a serial execution type user program automatically and at a high speed without re-coding, an object code is parallelized by detection of the possibility of parallel execution in an iteration unit of a loop, detection of the possibility of parallel execution of each statement in the loop, the interchange of an outer loop by an inner loop of a multiple loop, reduction of the multiple loop to a single loop, inclined coversion for making parallel execution along a wave front plane (line) when sufficient multiplicity is not derived, and the program which is estimated to have the shortest processing time is selected from the granularity, and multiplicity of the object code, the variance of the number of instructions and the proportion of synchronization control at the time of parallelization of the object code.
    Type: Grant
    Filed: October 18, 1988
    Date of Patent: September 29, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Kyoko Iwasawa, Yoshikazu Tanaka, Shizuo Gotou
  • Patent number: 5109331
    Abstract: An induction variable contained in a definition formula for a variable in a loop is analyzed for a source program to be compiled in order to optimize the execution of the program. The induction variable is represented by a standard form expressed by a value (initial value) in a first interation of the loop and a value (increment) which is incremented for each iteration of the loop, and a subscript in an array in the loop is represented by linear coupling to the standard form. Whether the subscript assumes the same value in one or more iterations of the loop for a pair of arrays in the loop is checked to analyze the independency and dependency of the arrays in the loop.
    Type: Grant
    Filed: September 16, 1987
    Date of Patent: April 28, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Ishida, Yasusi Kanada, Shizuo Gotou
  • Patent number: 5067068
    Abstract: In a compiling method, whether a variable (induction variable)recurrsively defined during loop iteration is included in an iteratively executed loop portion of a source program is detected. If such a variable is detected, a computation program portion for calculating a value of the variable which the variable should have during loop iteration of an arbitrary loop iteration number is generated. A plurality of parallely executable object program portions each for executing one of a plurality of processing to be executed during loop iteration of a respective loop iteration number of the loop portion is generated. Each of the object program portions includes a portion for executing the generated computation program portion for a respective loop iteration number to calculate a value of the variable for that loop iteration number.
    Type: Grant
    Filed: June 2, 1988
    Date of Patent: November 19, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Kyoko Iwasawa, Yoshikazu Tanaka, Shizuo Gotou
  • Patent number: 4876646
    Abstract: An information processing system including a group of translation tables in a multilevel structure for achieving address translation from a virtual address into a real address, a control register for keeping a starting point address data of a translation table located at a highest level among the address translation tables and a level data indicating a level (n) of the translation table at the highest level among the group of translation tables, and a unit for sequentially accessing the address translation tables at levels lower than the level (n) indicated by the level data in the control register based on the starting point address data and a virtual address to be translated, thereby translating the virtual address into a real address.
    Type: Grant
    Filed: December 18, 1985
    Date of Patent: October 24, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Shizuo Gotou, Toyohiko Kagimasa, Seiichi Yoshizumi
  • Patent number: 4807126
    Abstract: A method for converting a source program having a loop including a control statement into an object program including the steps of detecting from the statements of a first loop of a source program a control statement (an inductive control statement) having a control expression; detecting based on the control expression a turning form indicating whether a change of a turning number representing a loop iteration count indicates changes from values for a successful branch to values for an unsuccessful branch or vice versa and a turning point type indicating whether the turning number is an initial iteration count, a final iteration count, or an intermediate iteration count of the first loop; generating a string of statements having a loop not including the control statement and generating an execution result identical to an execution result of the first loop based on the first loop, the turning number, the turning form and the turning point type detected on the control statement; and converting the generated str
    Type: Grant
    Filed: February 10, 1987
    Date of Patent: February 21, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Shizuo Gotou, Yasusi Kanada, Kyoko Iwasawa
  • Patent number: 4792897
    Abstract: An extended address translation equipment wherein an address translation buffer has entries each provided with a record of translation table addresses of each level, thereby eliminating the need for accessing the translation table up to a portion consistent with the virtual address.
    Type: Grant
    Filed: October 2, 1985
    Date of Patent: December 20, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Shizuo Gotou, Toyohiko Kagimasa
  • Patent number: 4679140
    Abstract: A mode register stores a mode bit for each of the general registers, an access circuit accesses the general registers and the mode register so that a general register designated by an instruction and a corresponding mode bit are read out together. A data use circuit or a data supply circuit connected to the general registers includes a circuit portion which effectively changes the significant bit length of the data read out of the designated general register or of the data to be written into the designated general register.
    Type: Grant
    Filed: December 21, 1984
    Date of Patent: July 7, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Shizuo Gotou, Toyohiko Kagimasa, Seiichi Yoshizumi, Yooichi Shintani