Patents by Inventor Shizuo Sawada
Shizuo Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7187027Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.Type: GrantFiled: January 18, 2006Date of Patent: March 6, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kohyama, Takashi Ohsawa, Shizuo Sawada
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Publication number: 20060124980Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.Type: ApplicationFiled: January 18, 2006Publication date: June 15, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Yusuke Kohyama, Takashi Ohsawa, Shizuo Sawada
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Patent number: 7023044Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.Type: GrantFiled: July 20, 2004Date of Patent: April 4, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kohyama, Takashi Ohsawa, Shizuo Sawada
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Patent number: 6846733Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.Type: GrantFiled: March 17, 2003Date of Patent: January 25, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kohyama, Takashi Ohsawa, Shizuo Sawada
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Publication number: 20040262771Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.Type: ApplicationFiled: July 20, 2004Publication date: December 30, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Yusuke Kohyama, Takashi Ohsawa, Shizuo Sawada
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Publication number: 20030178686Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.Type: ApplicationFiled: March 17, 2003Publication date: September 25, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Yusuke Kohyama, Takashi Ohsawa, Shizuo Sawada
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Patent number: 6551894Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.Type: GrantFiled: August 3, 2000Date of Patent: April 22, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kohyama, Takashi Ohsawa, Shizuo Sawada
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Patent number: 6252281Abstract: Silicon oxide layers are provided in a substrate. That part of the silicon oxide layer which is located in a memory cell section MC has a thickness. That part of the silicon oxide layer which is located in a peripheral circuit section PC has a thickness, which is less than the thickness. The memory cell section MC has transistors, each having a source region and a drain region which contact the silicon oxide layer. The peripheral circuit section PC has transistors, each having a source region and a drain region which are spaced apart from the silicon oxide layer. The transistors of the peripheral circuit section PC are provided in well regions. A back-gate bias is applied to the transistors of the peripheral circuit section PC through impurity layers.Type: GrantFiled: March 7, 1996Date of Patent: June 26, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Yamamoto, Shizuo Sawada
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Patent number: 6130450Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.Type: GrantFiled: September 27, 1996Date of Patent: October 10, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kohyama, Takashi Ohsawa, Shizuo Sawada
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Patent number: 5726475Abstract: A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.Type: GrantFiled: September 16, 1994Date of Patent: March 10, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Shizuo Sawada, Syuso Fujii, Masaki Ogihara
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Patent number: 5410169Abstract: There is provided a DRAM memory cell structure. The semiconductor structure includes a semiconductor substrate of a first conductivity type having a main surface, source and drain regions of a second conductivity type formed in the main surface area of the semiconductor substrate, word lines extending in a first plane direction and formed on those portions of the semiconductor substrate which respectively lie between the source and drain regions, capacitors each having one of the source and drain regions as a storage node electrode, and bit lines buried in the semiconductor substrate and electrically connected to the source or drain regions, respectively.Type: GrantFiled: February 22, 1993Date of Patent: April 25, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Yamamoto, Shizuo Sawada
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Patent number: 5374838Abstract: A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.Type: GrantFiled: September 24, 1992Date of Patent: December 20, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Shizuo Sawada, Syuso Fujii, Masaki Ogihara
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Patent number: 5356830Abstract: A semiconductor device and its manufacturing method are provided in which an epitaxial silicon layer is formed by a selective epitaxial growth method over a semiconductor substrate and a polysilicon layer is formed by an ordinary deposition method on the epitaxial silicon layer and these layers and are formed over a semiconductor device in a continuous process within the same furnace for a CVD apparatus.Type: GrantFiled: December 17, 1990Date of Patent: October 18, 1994Assignee: Kabushiki Kaisha TobshibaInventors: Susumu Yoshikawa, Shuichi Samata, Satoshi Maeda, Shizuo Sawada
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Patent number: 5324975Abstract: For increasing pattern density of cell regions in a semiconductor memory device including an array of dynamic memory cells, the cell regions for cell transistor pairs are provided in a semiconductor substrate so as to be crossed by one desired bit line and two word lines adjacent thereto, and the patterns of cell regions have a same direction. Contacts for electrically connecting each bit line to common regions of cell transistor pairs are provided on respective bit lines every desired pitch at positions where each bit line intersects with cell regions. These contacts of adjacent bit lines are successively shifted in a bit line direction by approximately 1/2.sup.n (n is natural numbers greater than or equal to 2) pitch.Type: GrantFiled: January 14, 1993Date of Patent: June 28, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Kumagai, Shizuo Sawada
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Patent number: 5302542Abstract: A semiconductor substrate according to the present invention includes a first semiconductor substrate of a first conductivity type, an insulating film selectively formed in the first semiconductor substrate to define an exposed surface region, and a second semiconductor substrate of a second conductivity type opposite to the first conductivity type being bonded to the first semiconductor substrate. A DRAM cell formed by using the semiconductor substrate includes a trench capacitor formed in the first semiconductor substrate through both the second semiconductor substrate and the exposed surface region, and a transfer transistor formed in the second semiconductor substrate.Type: GrantFiled: May 5, 1993Date of Patent: April 12, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Kishi, Shizuo Sawada
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Patent number: 5302844Abstract: According to the present invention, a lower electrode is formed on a semiconductor substrate and overgrows upward to form one electrode of a capacitor having a mushroom-shaped section. An insulation film is formed so as to at least cover the lower electrode. An upper electrode is formed so as to oppose the lower electrode and to cover at least the insulation film.Type: GrantFiled: February 9, 1993Date of Patent: April 12, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Mizuno, Shizuo Sawada
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Patent number: 5276343Abstract: A DRAM cell having a bit line constituted by a semiconductor layer. The DRAM cell comprises a semiconductor substrate of a first conductivity type having a main surface, an insulating film formed on the main surface, an opening formed in the insulating film to communicate with the substrate, and a bit line formed by a semiconductor layer of a second conductivity type formed on the insulating film and that portion of the substrate which is exposed through the opening.Type: GrantFiled: September 10, 1992Date of Patent: January 4, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Kumagai, Shizuo Sawada
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Patent number: 5260226Abstract: A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.Type: GrantFiled: August 12, 1992Date of Patent: November 9, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Shizuo Sawada, Syuso Fujii, Masaki Ogihara
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Patent number: 5238860Abstract: A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.Type: GrantFiled: January 3, 1992Date of Patent: August 24, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Shizuo Sawada, Syuso Fujii, Masaki Ogihara
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Patent number: 5210437Abstract: The present invention provides a semiconductor device having a well, formed in a semiconductor substrate by using a mask in which a mask pattern width of a portion corresponding to an opening diameter is equal to or less than twice the diffusion depth of the well layer, and a gate electrode formed to have the well layer as a channel region of a MOS transistor. The well formed in this manner has a substantially semi-circular section to facilitate impurity concentration control in the substrate surface. When a plurality of types of opening patterns having small pattern widths are formed in a single mask, MOS transistors having different threshold voltages can be formed in a single process.Type: GrantFiled: August 10, 1992Date of Patent: May 11, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Shizuo Sawada, Seiko Iwasaki