Patents by Inventor Shlomo Waser

Shlomo Waser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4402067
    Abstract: A bidirectional serially controlled programmable read-only memory has a serial input/output (I/O) port and a parallel I/O port. By selecting the appropriate control inputs, the instant invention can receive serial address or data information and output data to either the parallel or serial I/O ports. In a like manner, an address at the parallel I/O port can be utilized to generate output data in either a serial or parallel form. In general, the parallel I/O port will be utilized to transfer data to and from a microprocessor, whereas the serial I/O port will be utilized to transfer data to and from an external interface. By proper utilization of the control circuits and appropriate use of the control signals, data may be read from the bidirectional PROM in parallel form from the parallel I/O port or in serial form from the serial I/O port. In addition, data may be transferred from the serial I/O port to the parallel I/O port or from the parallel I/O port to the serial I/O port.
    Type: Grant
    Filed: February 21, 1978
    Date of Patent: August 30, 1983
    Inventors: William E. Moss, Shlomo Waser, Ury Priel
  • Patent number: 4238833
    Abstract: A bus organized 16.times.16 (or 8.times.8) high-speed digital bus-organized multiplier/divider for high-speed, low-power operation is implemented on a single semiconductor chip. Four working registers each of 16 (or 8) bits are used in the system. These registers are a multiplier register, a multiplicand and divisor register, a first accumulator register for storing the least significant half of a double length product after a multiplication of the remainder after a division operation, and a second accumulator register which stores the most significant half of the product after a multiplication or the quotient after a division operation. A decoder is connected to the multiplicand and multiplier registers to implement the Modified Booth Algorithm and to encode the 16 (or 8) multiplier digits. The system operates to shift the multiplier number through the multiplier register to a position where the Modified Booth Algorithm encoding takes place.
    Type: Grant
    Filed: March 28, 1979
    Date of Patent: December 9, 1980
    Assignee: Monolithic Memories, Inc.
    Inventors: Robert C. Ghest, John M. Birkner, Shlomo Waser, Hua T. Chua