Patents by Inventor Sho KODAMA
Sho KODAMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210288662Abstract: According to one embodiment, a compression device includes a dictionary based encoder, a second buffer, a comparator, and a compression data generator. The dictionary based encoder searches for second data at least partially matching first data from a first buffer, and acquires a first match position indicating a position of the second data in the first buffer and a match length indicating a matched length of the first and second data. The second buffer stores the previously acquired second match position with an index. The compression data generator generates first compressed data that includes the index assigned to the second match position in the second buffer and the match length when the first match position matches the second match position in the second buffer.Type: ApplicationFiled: September 2, 2020Publication date: September 16, 2021Applicant: Kioxia CorporationInventors: Youhei FUKAZAWA, Keiri NAKANISHI, Sho KODAMA, Masato SUMIYOSHI, Kohei OIKAWA, Daisuke YASHIMA, Takashi MIURA, Zheye WANG
-
Patent number: 11048622Abstract: According to one embodiment, a memory system includes a NAND flash memory that has a first area, a second area, and a third area, and a controller that controls data transfer between a host device and the memory system. The controller writes data transmitted from the host device to the first area by a first method of storing 1-bit data per memory cell, and at a first timing, reads at least a part of data stored in the first area to generate one unit data, compresses the unit data, and writes the compressed unit data to the second area. At a second timing, the controller decompresses the read compressed unit data from the second area, and writes the decompressed unit data to the third area by a second method of storing a plurality of bits of data per memory cell.Type: GrantFiled: August 23, 2019Date of Patent: June 29, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Sho Kodama
-
Patent number: 10853234Abstract: A memory controller controls first and second memory, and includes a control unit. In response to a first write command from a host, which designates a logical address for first data to be written to the first memory, the control unit determines whether mapping of the logical address is presently being managed in a first mode with a first cluster size or a second mode with a second cluster size that is smaller than the first cluster size, changes first mapping data for the logical address stored in a first table in the second memory, from the first cluster size to the second cluster size, if the mapping of the logical address is being managed in the first mode and the first mapping data can be compressed at a ratio lower than a first compression ratio, and writes the first data to a physical address of the first memory.Type: GrantFiled: August 31, 2017Date of Patent: December 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Sho Kodama
-
Publication number: 20200293439Abstract: According to one embodiment, a memory system includes a NAND flash memory that has a first area, a second area, and a third area, and a controller that controls data transfer between a host device and the memory system. The controller writes data transmitted from the host device to the first area by a first method of storing 1-bit data per memory cell, and at a first timing, reads at least a part of data stored in the first area to generate one unit data, compresses the unit data, and writes the compressed unit data to the second area. At a second timing, the controller decompresses the read compressed unit data from the second area, and writes the decompressed unit data to the third area by a second method of storing a plurality of bits of data per memory cell.Type: ApplicationFiled: August 23, 2019Publication date: September 17, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Sho KODAMA
-
Patent number: 10719395Abstract: According to one embodiment, a memory system includes an error mitigation encoder that executes error mitigation coding on write data to be stored in a processing target page of a non-volatile memory, a memory interface that writes the write data which has undergone the error mitigation coding in the processing target page of the non-volatile memory and reads the write data which has undergone the error mitigation coding from the processing target page as read data, an error mitigation decoder that performs error mitigation decoding on the read data read from the processing target page of the non-volatile memory, and an error mitigation coding rate deciding unit that decides an error mitigation coding rate of the error mitigation encoder and the error mitigation decoder on the basis of at least one of information indicating the processing target page and information indicating a device characteristic of the processing target page.Type: GrantFiled: September 4, 2018Date of Patent: July 21, 2020Assignee: Toshiba Memory CorporationInventors: Tokumasa Hara, Kejen Lin, Sho Kodama, Keiri Nakanishi, Kohei Oikawa
-
Patent number: 10489243Abstract: According to one embodiment, for first data, which is read from a nonvolatile memory, for which a first data translation is performed, a second data translation that is a reverse translation of the first data translation is performed. Next, for the first data for which the second data translation is performed, the first data translation is performed. In addition, the read first data is compared with the first data for which the first data translation is performed, and check information is generated based on a result of the comparison.Type: GrantFiled: September 15, 2017Date of Patent: November 26, 2019Assignee: Toshiba Memory CorporationInventors: Kazuki Inoue, Sho Kodama, Keiri Nakanishi, Kohei Oikawa, Youhei Fukazawa
-
Publication number: 20190294500Abstract: According to one embodiment, a memory system includes an error mitigation encoder that executes error mitigation coding on write data to be stored in a processing target page of a non-volatile memory, a memory interface that writes the write data which has undergone the error mitigation coding in the processing target page of the non-volatile memory and reads the write data which has undergone the error mitigation coding from the processing target page as read data, an error mitigation decoder that performs error mitigation decoding on the read data read from the processing target page of the non-volatile memory, and an error mitigation coding rate deciding unit that decides an error mitigation coding rate of the error mitigation encoder and the error mitigation decoder on the basis of at least one of information indicating the processing target page and information indicating a device characteristic of the processing target page.Type: ApplicationFiled: September 4, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventors: Tokumasa Hara, Kejen Lin, Sho Kodama, Keiri Nakanishi, Kohei Oikawa
-
Patent number: 10310806Abstract: To provide a technology capable of changing an output characteristic of music data more efficiently with a simpler operation irrespective of whether or not the music data is being played back, an audio controller (2) identifies a usage environment of a wireless speaker (1) from picked-up image data on an installation room of the wireless speaker (1). Then, an output characteristic suitable for the identified usage environment is selected, and the selected output characteristic is set as an output characteristic of music data to be output from the wireless speaker (1).Type: GrantFiled: March 15, 2016Date of Patent: June 4, 2019Assignee: D&M Holdings, Inc.Inventor: Sho Kodama
-
Patent number: 10291918Abstract: An image compression apparatus according to an embodiment includes a slope determiner and a compressor. The slope determiner determines slopes of linear lines calculated from a reference component and non-reference components. The reference component is one of a plurality of image components forming pixels included in an input image data. The non-reference components are other image components. The compressor generates a compressed image data in which a value of the reference component of each of the pixels in the input image data, the slopes, and representative values of the non-reference components are compressed.Type: GrantFiled: March 4, 2016Date of Patent: May 14, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Sho Kodama, Keiri Nakanishi
-
Patent number: 10275165Abstract: According to one embodiment, a control unit determines a first physical sector in which first data is to be written among a plurality of physical sectors based on first information that is based on a result of the first data translation and the device characteristics of the plurality of physical sectors. A write unit writes data for which a first data translation is performed into the first physical sector of a nonvolatile memory.Type: GrantFiled: March 3, 2017Date of Patent: April 30, 2019Assignee: Toshiba Memory CorporationInventors: Kazuki Inoue, Sho Kodama, Keiri Nakanishi
-
Patent number: 10204043Abstract: According to one embodiment, a memory controller includes a compression unit and a padding processing unit. The compression unit generates first compressed data and second compressed data by compressing first data and second data. The padding processing unit pads first padding data for the first compressed data in accordance with a first padding pattern and pads second padding data for the second compressed data in accordance with a second padding pattern.Type: GrantFiled: February 1, 2017Date of Patent: February 12, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Keiri Nakanishi, Sho Kodama, Kohei Oikawa, Kojiro Suzuki
-
Patent number: 10193579Abstract: According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.Type: GrantFiled: September 7, 2016Date of Patent: January 29, 2019Assignee: Toshiba Memory CorporationInventors: Keiri Nakanishi, Katsuyuki Nomura, Sho Kodama, Youhei Fukazawa, Kazuki Inoue, Kojiro Suzuki, Harutaka Goto
-
Publication number: 20180276114Abstract: A memory controller controls first and second memory, and includes a control unit. In response to a first write command from a host, which designates a logical address for first data to be written to the first memory, the control unit determines whether mapping of the logical address is presently being managed in a first mode with a first cluster size or a second mode with a second cluster size that is smaller than the first cluster size, changes first mapping data for the logical address stored in a first table in the second memory, from the first cluster size to the second cluster size, if the mapping of the logical address is being managed in the first mode and the first mapping data can be compressed at a ratio lower than a first compression ratio, and writes the first data to a physical address of the first memory.Type: ApplicationFiled: August 31, 2017Publication date: September 27, 2018Inventor: Sho KODAMA
-
Publication number: 20180260274Abstract: According to one embodiment, for first data, which is read from a nonvolatile memory, for which a first data translation is performed, a second data translation that is a reverse translation of the first data translation is performed. Next, for the first data for which the second data translation is performed, the first data translation is performed. In addition, the read first data is compared with the first data for which the first data translation is performed, and check information is generated based on a result of the comparison.Type: ApplicationFiled: September 15, 2017Publication date: September 13, 2018Inventors: Kazuki Inoue, Sho Kodama, Keiri Nakanishi, Kohei Oikawa, Youhei Fukazawa
-
Publication number: 20180253276Abstract: To provide a technology capable of changing an output characteristic of music data more efficiently with a simpler operation irrespective of whether or not the music data is being played back, an audio controller (2) identifies a usage environment of a wireless speaker (1) from picked-up image data on an installation room of the wireless speaker (1). Then, an output characteristic suitable for the identified usage environment is selected, and the selected output characteristic is set as an output characteristic of music data to be output from the wireless speaker (1).Type: ApplicationFiled: March 15, 2016Publication date: September 6, 2018Inventor: Sho Kodama
-
Patent number: 10061691Abstract: According to one embodiment, a controller writes first processed data acquired by a first process into a nonvolatile memory during a first period. The controller writes second processed data acquired by a second process into the nonvolatile memory during a second period. The first process is for the purpose of improving the endurance of memory cells. The second process is for the purpose of decreasing inter-cell interferences between adjacent cells.Type: GrantFiled: March 15, 2017Date of Patent: August 28, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kejen Lin, Tokumasa Hara, Hironori Uchikawa, Juan Shi, Akira Yamaga, Sho Kodama, Keiri Nakanishi
-
Patent number: 9971523Abstract: According to one embodiment, a memory controller includes a compression unit and a padding processing unit. The compression unit compresses first data to be written into a first page and second data to be written into a second page. The padding processing unit performs a padding processing such that the compressed first data is written into first memory cells, first padding data is written into second memory cells, the compressed second data is written into third memory cells, and second padding data is written into fourth memory cells.Type: GrantFiled: September 9, 2016Date of Patent: May 15, 2018Assignee: Toshiba Memory CorporationInventors: Sho Kodama, Keiri Nakanishi, Kohei Oikawa, Kojiro Suzuki
-
Publication number: 20180074730Abstract: According to one embodiment, a control unit determines a first physical sector in which first data is to be written among a plurality of physical sectors based on first information that is based on a result of the first data translation and the device characteristics of the plurality of physical sectors. A write unit writes data for which a first data translation is performed into the first physical sector of a nonvolatile memory.Type: ApplicationFiled: March 3, 2017Publication date: March 15, 2018Inventors: Kazuki Inoue, Sho Kodama, Keiri Nakanishi
-
Publication number: 20180068719Abstract: According to one embodiment, a controller writes first processed data acquired by a first process into a nonvolatile memory during a first period. The controller writes second processed data acquired by a second process into the nonvolatile memory during a second period. The first process is for the purpose of improving the endurance of memory cells. The second process is for the purpose of decreasing inter-cell interferences between adjacent cells.Type: ApplicationFiled: March 15, 2017Publication date: March 8, 2018Applicant: Toshiba Memory CorporationInventors: Kejen LIN, Tokumasa HARA, Hironori UCHIKAWA, Juan SHI, Akira YAMAGA, Sho KODAMA, Keiri NAKANISHI
-
Patent number: 9792884Abstract: According to one embodiment, an image processing apparatus includes an encoding unit that compresses an input image for each pixel block having a size smaller than a line to generate a plurality of compressed blocks, and store the compressed blocks in a frame buffer, a reading unit that identifies an object block to be expanded among the compressed blocks, and reads the object block from the frame buffer, a decoding unit that expands the object block to generate an expanded block, and an information acquiring unit that acquires, based on the expanded block, position information used by the reading unit to identify the block to be expanded, or decode information used by the decoding unit to expand another compressed block.Type: GrantFiled: January 5, 2016Date of Patent: October 17, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Youhei Fukazawa, Keiri Nakanishi, Masashi Jobashi, Sho Kodama