Abstract: Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types.

Abstract: Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively.

Abstract: A system and method is provided for variable bit rate encoding using a complexity ratio. Quantization parameter is calculated using a complexity ratio, which is equal to a local complexity divided by a global complexity. Complex pictures are allocated a larger bit budget relative to simple pictures. With the larger bit budget the quality of complex pictures can be maintained while reducing the overall size of the encoded video stream.

Abstract: A method and system is provided for calculating motion vectors of macroblocks in a digital image of a digital video stream. The method and system reduces the computational overhead of calculating motion vectors computing difference measures using a predetermined pattern of pixels in each macroblock rather than all the pixels of the macroblock. Reduction of computational overhead can be further enhanced first using a subpattern, i.e., a sub-sample of the predetermined pattern on a subset of the macroblocks to determine close matching macroblocks and then using the predetermined pattern to determine the best matching macroblock from within the close matching macroblocks.

Abstract: A method and system is provided for calculating motion vectors of macroblocks in a digital image of a digital video stream. The method and system reduces the computational overhead of calculating motion vectors computing difference measures using a multi-phase computational scheme. Specifically, the pixel blocks the previous image are divided into different groups. The closest matching pixel block of each group is determined in a first phase. Then a more accurate difference measure is used to determine the origin block from among the closest matching pixel blocks.

Abstract: A method and system is provided for calculating motion vectors of macroblocks in a digital image of a digital video stream. The method and system reduces the computational overhead of calculating motion vectors by limiting the search for the origin block to a coarse search window and a fine search window within the coarse search window. The difference measure is computed for only a subset of pixel blocks within the coarse search window to reduce the computational overhead. However, to increase accuracy, the difference measure of all the pixel blocks in the fine search window are computed. The pixel block having the smallest difference measure is selected as the origin block.

Abstract: A method and system is provided for encoding a digital video stream, which requires less computation overhead as compared to conventional systems. Specifically, the encoded digital video stream includes direct mode predicted frames in place of some of the standard predicted frames. The direct mode predicted frames are formed without computing motion vectors for each macro-block of the direct mode predicted frame. During decoding, motion vectors from a co-located macro-block of a preceding predicted frame is copied and applied to each macro-block of the direct mode predicted frame. Because computing motion vectors is generally the most computing intensive task of encoding digital video streams, the use of direct mode predicted frames can greatly reduce the computation requirements for encoding digital video streams.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA?23:0!) and second (RA?31:24!) subsets, and a shadow subset (RT?31:24!). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively.

Abstract: An apparatus and method for determining inter-frame motion during compression of digital video data incorporates a computationally efficient hierarchical block-matching motion estimation technique in conjunction with a full-search block-matching approach. In the hierarchical block-matching method, a macroblock is filtered and decimated, and a search area is also filtered and decimated. A block-matching search is performed within the filtered and decimated search area. An augmented block in the original search area that corresponds to the block in the decimated search area that provided the best match with the decimated macroblock is then compared with the original macroblock to determine a motion vector. Operating parameters specify the search range based on the type of frame being processed, i.e. P-frame or B-frame, and, in the case of B-frames, the distance of the B-frame from the reference frame.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA?23:0!) and second (RA?31:24!) subsets, and a shadow subset (RT?31:24!). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively.